"Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and ..."

Mingjie Liu et al. (2021)

> Home

Details and statistics

DOI: 10.23919/DATE51398.2021.9474253

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/date/LiuTKKPR21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/LiuTKKPR21
Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren:
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. DATE 2021: 1372-1377

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.