"647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA."

Benjamin Stefan Devlin et al. (2009)

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DOI: 10.1109/ESSCIRC.2009.5326010

access: closed

type: Conference or Workshop Paper

metadata version: 2020-07-07

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Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC 2009: 156-159

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