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"A level shifter with logic error correction circuit for extremely ..."

Yuji Osaki et al. (2011)

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DOI: 10.1109/ESSCIRC.2011.6044899

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC 2011: 199-202

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