"Optimization of Testability of Sequential Circuits Implemented in FPGAs ..."

Andrzej Krasniewski (2004)

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DOI: 10.1007/978-3-540-30117-2_128

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Andrzej Krasniewski:
Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. FPL 2004: 1067-1072

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