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ORCID"Logic synthesis for low power using clock gating and rewiring."
Tak-Kei Lam et al. (2010)
- Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu:
Logic synthesis for low power using clock gating and rewiring. ACM Great Lakes Symposium on VLSI 2010: 179-184
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