research-article

Logic synthesis for low power using clock gating and rewiring

Authors:

Wai-Chung Tang,

Yu-Liang WuAuthors Info & Claims

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

Pages 179 - 184

https://doi.org/10.1145/1785481.1785527

Published: 16 May 2010 Publication History

Abstract

Traditionally, clock gating for power saving is mainly done at Register Transistor Level (RTL), while in a lower logical level some synthesis techniques, e.g. Observability Don't Care (ODC) can also be used to provide more power savings. In this paper, we propose an effective logic level ODC-based clock gating scheme that aims to reduce the intra-module dynamic power of sequential circuits. It is accompanied with a rewiring-based pruning scheme to trim down the incurred area overhead. Switching activity is put into account in the optimization processes. Extensive experimental results obtained by using ModelSim and PowerCompiler on the ISCAS-89 benchmarks showed that without rewired area trimming, an average of 40% on clock power and 12% on total dynamic power can be saved with a total cell area overhead of 6%. When rewiring was applied to trim down the area overhead, a similar clock power saving of 40% and an appealing 17% of total dynamic power saving can be achieved with area similar (-1%) to the original non ODC-clock-gated circuits.

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Cited By

Lam TTang WWei XDiao YYu‐LiangWu D(2016)ApplicationsBoolean Circuit Rewiring10.1002/9781118750124.ch5(133-210)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781118750124.ch5
Shenming WSuntiamorntut WJindapetch NJi Qiufan (2011)Scheduling & resources sharing technique for adaptive LMS filterThe 8th Electrical Engineering/ Electronics, Computer, Telecommunications and Information Technology (ECTI) Association of Thailand - Conference 201110.1109/ECTICON.2011.5947784(114-117)Online publication date: May-2011
https://doi.org/10.1109/ECTICON.2011.5947784

Index Terms

Logic synthesis for low power using clock gating and rewiring
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
      1. Circuit optimization

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cover image ACM Conferences

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

May 2010

502 pages

ISBN:9781450300124

DOI:10.1145/1785481

General Chairs:
R. Iris Bahar
Brown University, USA
,
Fabrizio Lombardi
Northeastern University, USA
,
Program Chairs:
David Atienza
EPFL, Switzerland
,
Erik Brunvand
University of Utah, USA

Copyright © 2010 ACM.

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Published: 16 May 2010

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GLSVLSI '10: Great Lakes Symposium on VLSI 2010

May 16 - 18, 2010

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Cited By

Lam TTang WWei XDiao YYu‐LiangWu D(2016)ApplicationsBoolean Circuit Rewiring10.1002/9781118750124.ch5(133-210)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781118750124.ch5
Shenming WSuntiamorntut WJindapetch NJi Qiufan (2011)Scheduling & resources sharing technique for adaptive LMS filterThe 8th Electrical Engineering/ Electronics, Computer, Telecommunications and Information Technology (ECTI) Association of Thailand - Conference 201110.1109/ECTICON.2011.5947784(114-117)Online publication date: May-2011
https://doi.org/10.1109/ECTICON.2011.5947784

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