research-article

Circuit Optimization by Rewiring

Authors:

Shih-Chieh Chang,

Lukas P. P. P. van Ginneken, and

Malgorzata Marek-SadowskaAuthors Info & Claims

IEEE Transactions on Computers, Volume 48, Issue 9

Pages 962 - 970

https://doi.org/10.1109/12.795224

Published: 01 September 1999 Publication History

Abstract

This paper presents a very efficient optimization method suitable for multilevel combinational circuits. The optimization is based on incremental restructuring of a circuit through a sequence of additions and removals of redundant wires. Our algorithm applies the techniques of Automatic Test Pattern Generation (ATPG), which can efficiently detect redundancies. During the ATPG process, certain nodes in the circuit must have particular logic assignments for a test to exist. Based on the properties of these mandatory assignments, we have developed theorems to eliminate unnecessary wire redundancy checking. This results in significant performance improvement. The fast run time and the excellent scaling to large circuits make our Boolean optimization method practical for industrial applications.

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Cited By

Neto WAmarú LPossani VVuillod PLuo JMishchenko AGaillardon POshana R(2022)Improving LUT-based optimization for ASICsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530461(421-426)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530461
Amarú LPossani VTesta EMarranghello FCasares CLuo JVuillod PMishchenko ADe Micheli G(2021)LUT-Based Optimization For ASIC Design Flow2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586132(871-876)Online publication date: 5-Dec-2021
https://dl.acm.org/doi/10.1109/DAC18074.2021.9586132
Chen Y(2018)Enhancements to SAT AttackACM Transactions on Design Automation of Electronic Systems10.1145/319085323:4(1-25)Online publication date: 9-May-2018
https://dl.acm.org/doi/10.1145/3190853
Show More Cited By

Index Terms

Circuit Optimization by Rewiring
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 48, Issue 9

September 1999

140 pages

ISSN:0018-9340

Editor:
Jean-Luc Gaudiot
Univ. of Southern California, Los Angeles

Issue’s Table of Contents

Copyright © Copyright © 1999 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 September 1999

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Cited By

Neto WAmarú LPossani VVuillod PLuo JMishchenko AGaillardon POshana R(2022)Improving LUT-based optimization for ASICsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530461(421-426)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530461
Amarú LPossani VTesta EMarranghello FCasares CLuo JVuillod PMishchenko ADe Micheli G(2021)LUT-Based Optimization For ASIC Design Flow2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586132(871-876)Online publication date: 5-Dec-2021
https://dl.acm.org/doi/10.1109/DAC18074.2021.9586132
Chen Y(2018)Enhancements to SAT AttackACM Transactions on Design Automation of Electronic Systems10.1145/319085323:4(1-25)Online publication date: 9-May-2018
https://dl.acm.org/doi/10.1145/3190853
Lin CWang CChen YHuang CFettweis GNebel W(2014)Rewiring for threshold logic circuit minimizationProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616754(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616754
Yang XLam TTang WWu YRosenstiel WMacii E(2012)Almost every wire is removableProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493092(1573-1578)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493092
Lam TTang WYang XWu Y(2012)ECRACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885417:4(1-21)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348854
Wei XTang WWu YSze CAlpert CBrunvard EStevens KCavallaro JZhang T(2012)WRIPProceedings of the great lakes symposium on VLSI10.1145/2206781.2206861(327-332)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206861
Yang XLam TWu YSapatnekar S(2010)ECRProceedings of the 47th Design Automation Conference10.1145/1837274.1837400(511-516)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837400
Lam TYang STang WWu YBahar RLombardi FAtienza DBrunvand E(2010)Logic synthesis for low power using clock gating and rewiringProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785527(179-184)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785527
Xiang HRen HTrevillyan LReddy LPuri RCho MSaxena PChang Y(2010)Logical and physical restructuring of fan-in treesProceedings of the 19th international symposium on Physical design10.1145/1735023.1735046(67-74)Online publication date: 14-Mar-2010
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