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Sequential logic optimization by redundancy addition and removal

Authors:

Luis Entrena,

Kwang-Ting ChengAuthors Info & Claims

ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Pages 310 - 315

Published: 07 November 1993 Publication History

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Kravets VMishchenko ABenini LDe Micheli GAl-Hashimi BMueller W(2009)Sequential logic synthesis using symbolic bi-decompositionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874970(1458-1463)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874970
Zhou CTang WLo WWu YLevitan S(2007)How much can logic perturbation help from netlist to final routing for FPGAsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278707(922-927)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278707
Wu YCheung CCheng DFan H(2003)Further improve circuit partitioning using GBAW logic perturbation techniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81236911:3(451-460)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.812369
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Sequential logic optimization by redundancy addition and removal
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ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

November 1993

781 pages

ISBN:0818644907

Chairmen:
Michael Lightner
Univ. of Colorado, Boulder
,
Jochen A. G. Jess
Eindhoven Univ. of Tech., Eindhoven, The Netherlands

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IEEE Computer Society Press

Washington, DC, United States

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Published: 07 November 1993

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ICCAD '93: International Conference on Computer Aided Design

November 7 - 11, 1993

California, Santa Clara, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Kravets VMishchenko ABenini LDe Micheli GAl-Hashimi BMueller W(2009)Sequential logic synthesis using symbolic bi-decompositionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874970(1458-1463)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874970
Zhou CTang WLo WWu YLevitan S(2007)How much can logic perturbation help from netlist to final routing for FPGAsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278707(922-927)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278707
Wu YCheung CCheng DFan H(2003)Further improve circuit partitioning using GBAW logic perturbation techniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81236911:3(451-460)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.812369
Pilarski SHu GAckland B(2002)SAT with partial clauses and back-leapsProceedings of the 39th annual Design Automation Conference10.1145/513918.514104(743-746)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.514104
Sinha SKuehlmann ABrayton RErnst R(2001)Sequential SPFDsProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603113(84-90)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603113
Espejo JEntrena LSan Millán EOlias E(2001)Generalized reasoning scheme for redundancy addition and removal logic optimizationProceedings of the conference on Design, automation and test in Europe10.5555/367072.367281(391-397)Online publication date: 13-Mar-2001
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Sze CWu YGoto S(2001)Improved alternative wiring scheme applying dominator relationshipProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370515(473-478)Online publication date: 30-Jan-2001
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Espejo JEntrena LSan Millán EOliás EGoto S(2001)Functional extension of structural logic optimization techniquesProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370514(467-472)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370514
(2000)Binary and Multi-Valued SPFD-Based Wire Removal in PLA NetworksProceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors10.5555/557517.846911Online publication date: 17-Sep-2000
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Marques-Silva JSakallah KDe Micheli G(2000)Boolean satisfiability in electronic design automationProceedings of the 37th Annual Design Automation Conference10.1145/337292.337611(675-680)Online publication date: 1-Jun-2000
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Combinational and sequential logic optimization by redundancy addition and removal

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Combinational and sequential logic optimization by redundancy addition and removal

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

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