"Low Voltage Clock Tree Synthesis with Local Gate Clusters."

Can Sitik et al. (2019)

> Home

Details and statistics

DOI: 10.1145/3299874.3318004

access: closed

type: Conference or Workshop Paper

metadata version: 2019-05-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/SitikLTS19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/SitikLTS19
Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman:
Low Voltage Clock Tree Synthesis with Local Gate Clusters. ACM Great Lakes Symposium on VLSI 2019: 99-104

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.