"VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow."

Fabrizio Ferrandi et al. (2006)

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DOI: 10.1109/IPDPS.2006.1639491

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco D. Santambrogio:
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. IPDPS 2006

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