"Variable-latency adder (VL-adder): new arithmetic circuit design practice ..."

Yiran Chen et al. (2007)

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DOI: 10.1145/1283780.1283822

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-04

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Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh:
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200

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