"Deep Neural Network Training Accelerator Designs in ASIC and FPGA."

Shreyas K. Venkataramanaiah et al. (2020)

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DOI: 10.1109/ISOCC50952.2020.9333063

access: closed

type: Conference or Workshop Paper

metadata version: 2021-02-12

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Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-Sun Seo:
Deep Neural Network Training Accelerator Designs in ASIC and FPGA. ISOCC 2020: 21-22

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