"Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits."

Ching-Te Chuang et al. (2003)

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DOI: 10.1109/ISQED.2003.1194724

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim:
Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158

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