"A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With ..."

David Bol et al. (2019)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2019.8662293

access: closed

type: Conference or Workshop Paper

metadata version: 2023-10-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/BolSMHXFDSF19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/BolSMHXFDSF19
David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre:
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. ISSCC 2019: 322-324

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.