"A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms ..."

Wooseok Kim et al. (2013)

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DOI: 10.1109/ISSCC.2013.6487721

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.032mm² 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. ISSCC 2013: 250-251

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