"A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy."

Naveen Verma, Anantha P. Chandrakasan (2007)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2007.373427

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/VermaC07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/VermaC07
Naveen Verma, Anantha P. Chandrakasan:
A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy. ISSCC 2007: 328-606

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.