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"Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate ..."

Solomon Michael Serunjogi et al. (2017)

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DOI: 10.1109/VLSI-SOC.2017.8203490

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-22

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  - conf/vlsi/SerunjogiLRS17
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Solomon Michael Serunjogi, Kai-Wei Lin, Mahmoud Rasras, Mihai Sanduleanu:
Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector. VLSI-SoC 2017: 1-6

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