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"A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of ..."

Wei-Chih Chen et al. (2019)

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DOI: 10.23919/VLSIC.2019.8777992

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

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Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh:
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET. VLSI Circuits 2019: 272-

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