"0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay ..."

Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani (2008)

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DOI: 10.1109/VLSI.2008.95

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani:
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2008: 613-619

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