"A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM ..."

Vinay Kumar et al. (2017)

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DOI: 10.1109/VLSID.2017.17

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Vinay Kumar, Nikhil Puri, Sudhir Kumar, Sumit Srivastav:
A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET. VLSID 2017: 269-274

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