"Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis."

Sajib Kumar Mitra, Ahsan Raja Chowdhury (2012)

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DOI: 10.1109/VLSID.2012.93

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Sajib Kumar Mitra, Ahsan Raja Chowdhury:
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis. VLSI Design 2012: 334-339

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