"A speed-enhanced DRAM array architecture with embedded ECC."

Kazutami Arimoto et al. (1990)

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DOI: 10.1109/4.50277

access: closed

type: Journal Article

metadata version: 2025-01-23

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Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima:
A speed-enhanced DRAM array architecture with embedded ECC. IEEE J. Solid State Circuits 25(1): 11-17 (1990)

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