"A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With ..."

Yen-Huei Chen et al. (2009)

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DOI: 10.1109/JSSC.2009.2014208

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type: Journal Article

metadata version: 2024-02-05

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Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi:
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. IEEE J. Solid State Circuits 44(4): 1209-1215 (2009)

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