"A 28 GHz Hybrid PLL in 32 nm SOI CMOS."

Mark A. Ferriss et al. (2014)

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DOI: 10.1109/JSSC.2014.2299273

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type: Journal Article

metadata version: 2020-08-30

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Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman:
A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J. Solid State Circuits 49(4): 1027-1035 (2014)

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