"A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and ..."

Yasuhiro Takai et al. (2000)

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DOI: 10.1109/4.823441

access: closed

type: Journal Article

metadata version: 2022-04-08

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Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda:
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. IEEE J. Solid State Circuits 35(2): 149-162 (2000)

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