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"Efficient Hardware Design of Iterative Stencil Loops."

Vincenzo Rana et al. (2016)

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DOI: 10.1109/TCAD.2016.2545408

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - https://dblp.org/rec/journals/tcad/RanaBBNAS16
Vincenzo Rana, Ivan Beretta, Francesco Bruschi, Alessandro Antonio Nacci, David Atienza, Donatella Sciuto:
Efficient Hardware Design of Iterative Stencil Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2018-2031 (2016)

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