"Power and latency efficient mechanism: a seamless bridge between buffered ..."

Jing Lin, Xiaola Lin (2012)

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DOI: 10.1007/S11227-011-0676-3

access: closed

type: Journal Article

metadata version: 2020-05-22

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Jing Lin, Xiaola Lin:
Power and latency efficient mechanism: a seamless bridge between buffered and bufferless routing in on-chip network. J. Supercomput. 61(3): 1048-1067 (2012)

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