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ORCIDISCAS 2001: Sydney, Australia - Volume 4
- Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001. IEEE 2001, ISBN 0-7803-6685-9
- Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. 1-4 - A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz
:
Testing complementary pass-transistor logic circuits. 5-8 - San Lin, Samiha Mourad, Shoba Krishnan:
At-speed testing of data communications transceivers. 9-12 - Shyue-Kung Lu, Chih-Hsien Hsu:
Built-In self-repair for divided word line memory. 13-16 - Abdelhakim Khouas, Anne Derieux:
FDP: fault detection probability function for analog circuits. 17-20 - Zahir M. Hussain, Boualem Boashash:
Statistical analysis of the time-delay digital tanlock loop in the presence of Gaussian noise. 21-24 - Tung-Sang Ng, Kun-Wah Yip, Chin-Long Cheng:
An all-lag rotating-reference correlator and its efficient implementation. 25-28 - Ki-Cheol Tae, Jin-Gyun Chung, Dae-Ik Kim:
Noise generation system using DCT. 29-32 - Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. 33-36 - Johann Großschädl:
A low-power bit-serial multiplier for finite fields GF(2m). 37-40 - Andrew C. McCormick, Peter M. Grant, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan:
A low power MMSE receiver architecture for multi-carrier CDMA. 41-44 - Ulrich Walther, Gerhard P. Fettweis:
PN-generators embedded in high performance signal processors. 45-48 - Tetsuya Shimamura:
Nonuniform amplitude division for ABLMS equalisation. 49-52 - Daniel León, Sina Balkir, Michael W. Hoffman, Lance C. Pérez:
Robust chaotic PN sequence generation techniques. 53-56 - Yeong-Kang Lai, Yu-Chuan Shu:
VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation. 57-60 - David Garrett, Mircea R. Stan:
A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications. 61-64 - Zhipei Chi, Leilei Song, Keshab K. Parhi:
A study on the performance, complexity tradeoffs of block turbo decoder design. 65-68 - Håkan Bengtson, Christer Svensson:
3V CMOS 0.35 µ transimpedance receiver for optical applications. 69-71 - Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu:
A serial link transceiver for USB2 high-speed mode. 72-75 - Inseop Lee, W. Kenneth Jenkins:
Pipelined implementation of the adaptive canceller-equalizer. 76-80 - Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang:
A 1.25 GHz 32-bit tree-structured carry lookahead adder. 80-83 - Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour:
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. 84-87 - Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang:
A high-speed CMOS incrementer/decrementer. 88-91 - Andreas Wassatsch, Dirk Timmermann:
Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. 92-95 - Juan A. Montiel-Nelson, De de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi:
A compact layout technique to minimize high frequency switching effects in high speed circuits. 96-99 - Hossein Zarei, Omid Shoaei, Seid Mehdi Fakhraie:
A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis. 100-103 - Xiaohong Sun, Kenneth R. Laker:
A new design for cascaded sigma-delta modulators. 104-107 - Burkart Voss, Manfred Glesner:
A low power sinusoidal clock. 108-111 - Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
CML ring oscillators: oscillation frequency. 112-115 - Yijun Zhou, Jiren Yuan:
An 8-Bit, 100-MHz low glitch interpolation DAC. 116-119 - F. Xavier Moncunill-Geniz, Orestes Mas-Casals, Pere Palà-Schönwälder:
A comparative analysis of direct-sequence spread-spectrum super-regenerative architectures. 120-123 - Kari Stadius, Petri Järviö, Petteri Paatsila, Kari Halonen:
Image-reject receivers with image-selection functionality. 124-127 - Sridhar Rajagopal, Joseph R. Cavallaro:
A bit-streaming, pipelined multiuser detector for wireless communication receivers. 128-131 - Frank S. Tsai, Chen-Yi Lee:
A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system. 132-135 - Satoshi Makido, Takaya Yamazato, Hiraku Okada, Masaaki Katayama, Akira Ogawa:
A design of source matched MAP receiver for image transmission. 136-139 - Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni:
A CMOS differential logic for low-power and high-speed applications. 140-143 - Frank Grassert, Dirk Timmermann:
Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs. 144-147 - Hongchin Lin, Yi-Fan Chen, Hsien-Chih She:
A low-power 3-phase half rail pass-gate differential logic. 148-151 - K. Y. Cheung:
CRRDL: a novel charge recovery-recycling differential logic. 152-153 - Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic. 154-157 - Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic. 158-161 - Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis:
The circuit design of multiple-valued logic voltage-mode adders. 162-165 - Henrik Eriksson, Per Larsson-Edefors, William P. Marnane:
A regular parallel multiplier which utilizes multiple carry-propagate adders. 166-169 - Pasi Liljeberg, Juha Plosila, Jouni Isoaho:
Asynchronous interface for locally clocked modules in ULSI systems. 170-173 - Nazmy Abaskharoun, Mohamed M. Hafed, Gordon W. Roberts:
Strategies for on-chip sub-nanosecond signal capture and timing measurements. 174-177 - Wen-Tsong Shiue:
Leakage power estimation and minimization in VLSI circuits. 178-181 - Huo-Hsing Cheng, Ven-Chieh Hsieh:
A new logic synthesis and optimization procedure. 182-185 - Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek:
Minimizing gate capacitances with transistor sizing. 186-189 - Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A low-cost CMOS time interval measurement core. 190-193 - Tero Säntti, Jouni Isoaho:
Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units. 194-197 - Felix Lustenberger, Hans-Andrea Loeliger:
On mismatch errors in analog-VLSI error correcting decoders. 198-201 - Tong Zhang, Zhongfeng Wang, Keshab K. Parhi:
On finite precision implementation of low density parity check codes decoder. 202-205 - Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders. 206-209 - Mario Träber:
A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros. 210-213 - Mario Träber:
A low power survivor memory unit for sequential Viterbi-Decoders. 214-217 - Youngjoon Kim, Lee-Sup Kim:
A low power carry select adder with reduced area. 218-221 - Viv A. Bartlett, Andrew G. Dempster:
Using carry-save adders in low-power multiplier blocks. 222-225 - Ayman A. Fayed, Magdy A. Bayoumi:
A low power 10-transistor full adder cell for embedded architectures. 226-229 - Gang Xu, Jiren Yuan:
An embedded low power FIR filter. 230-233 - Stephan Klauke, Jürgen Götze:
Low power enhancements for parallel algorithms. 234-237 - Kasin Vichienchom, Mark Clements, Wentai Liu:
A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique. 238-241 - Raj K. Jain, R. Frenzel, M. Terschluse, Pramod K. Pandey, Seo H. Low, Biju Sukumaran, Lup M. Lam:
System-on-chip design of a four-port ADSL-lite Data DSP. 242-245 - Yuyu Chang, Jack Wills, John Choma Jr.:
On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters. 246-249 - Chi-Li Yu, An-Yeu Wu:
An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. 250-253 - Scott D. Huss, John Bennett:
An efficient model for twisted-pair cables with discontinuities and stubs for discrete time simulations. 254-257 - John C. McEachen, Ow Kong Chung, Lim Chin Thong:
A system level description and model of Signaling System No 7. 258-261 - Wael M. Badawy, Magdy A. Bayoumi:
A mesh based motion tracking architecture. 262-265 - Jin-Ku Kang, Dong-Hee Kim:
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. 266-269 - B. Siddik Yarman, Ahmet Aksen:
A reflectance-based computer aided modelling tool for high speed/high frequency communication systems. 270-273 - Ronald P. Luijten, Antonius P. J. Engbersen, Cyriel Minkenberg:
Shared memory switching + virtual output queuing: A robust and scalable switch. 274-277 - Mostafa I. H. Abd-El-Barr, C. Sundarram, A. S. Almulhem:
VLSI considerations in the design of k-ary n-cube interconnection networks. 278-281 - Di He, Chen He, Ling-ge Jiang, Hong-Wen Zhu, Guang-Rui Hu:
Phase tracking of CDMA spreading sequences using dynamic chaotic synchronization. 282-285 - Chin-Liang Wang, Ming-Hung Li, Kuo-Ming Wu, Kwei-Liang Hwang:
Adaptive interference suppression with power control for CDMA systems. 286-289 - Kyungtae Han, Iksu Eo, Kyungsu Kim, Hanjin Cho:
Numerical word-length optimization for CDMA demodulator. 290-293 - Jing Lei, Tung-Sang Ng:
New AFC algorithm for a fully-digital MDPSK DS/CDMA receiver. 294-297 - Xianmin Wang, Wu-Sheng Lu, Andreas Antoniou:
A near-optimal multiuser detector for CDMA channels using semidefinite programming relaxation. 298-301 - Yann Bajot, Habib Mehrez:
Customizable DSP architecture for ASIP core design. 302-305 - Tuomas Järvinen, Jarmo Takala, David Akopian, Jukka Saarinen:
Register-based multi-port perfect shuffle networks. 306-309 - Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig:
Self-reorganising systems on VLSI circuits. 310-313 - Siamak Mortezapour, Edward K. F. Lee:
A reconfigurable pipelined data converter. 314-317 - Akil E. Bashagha:
Novel radix-2k division algorithm. 318-321 - Jee G. Lim, Cheng-Chew Lim:
A parallel architecture for estimating 4th-order cumulants. 322-325 - Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee:
Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission. 326-329 - Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee:
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. 330-333 - Christos Drosos, Chrissavgi Dre, Spyros Blionas, Dimitrios Soudris:
On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal. 334-337 - Li-Hsun Chen, Oscal T.-C. Chen:
A low-complexity and high-speed Booth-algorithm FIR architecture. 338-341 - Adel-Omar Dahmane, Daniel Massicotte, Leszek Szczecinski:
A VLSI architecture of a piecewise RBF decision feedback channel equalizer. 342-345 - Shyue-Win Wei:
Cellular-array power-sum circuits over programmable finite field GF(2'''). 346-349 - Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono:
FPGA realization of RNS to binary signed conversion architecture. 350-353 - Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu:
Design and implementation of channel equalizers for block transmission systems. 354-357 - Ching-Chi Chang, Chien-Chih Lin, Muh-Tian Shiue, Chorng-Kuang Wang:
A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop. 358-361 - Waleed M. Younis, Naofal Al-Dhahir:
FIR prefilter design for MLSE equalization of space-time-coded transmission over multipath fading channels. 362-365 - Roberto López-Valcarce, Soura Dasgupta:
Second order statistics based blind channel equalization with correlated sources. 366-369 - Ediz Çetin, Izzet Kale, Richard C. S. Morling:
Adaptive compensation of analog front-end I/Q mismatches in digital receivers. 370-373 - Xiaopeng Li, Mohammed Ismail:
A single-chip CMOS front-end receiver architecture for multi-standard wireless applications. 374-377 - Tang Jing Jung, King Sau Cheung, Jack Lau:
A 2.4 GHz four port mixer for direct conversion used in telemetering. 378-381 - Kalle Kivekäs, Aarno Pärssinen, Jarkko Jussila, Jussi Ryynänen, Kari Halonen:
Design of low-voltage active mixer for direct conversion receivers. 382-385 - Zhaofeng Zhang, Louis Tsui, Zhiheng Chen, Jack Lau:
A CMOS self-mixing-free front-end for direct conversion applications. 386-389 - Hung Yan Cheung, King Sau Cheung, Jack Lau:
A low power monolithic AGC with automatic DC offset cancellation for direct conversion hybrid CDMA transceiver used in telemetering. 390-393 - Harri Lampinen, Olli Vainio:
Dynamically biased current sensor for current-sensing completion detection. 394-397 - Yavuz Kiliç, Mark Zwolinski:
Process variation independent built-in current sensor for analogue built-in self-test. 398-401 - Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti:
Modeling and minimization of power consumption in charge pump circuits. 402-405 - Sheng-Yeh Lai, Jinn-Shyan Wang:
A high-efficiency CMOS charge pump circuit. 406-409 - Joshua L. Garrett, Mircea R. Stan:
Active threshold compensation circuit for improved performance in cooled CMOS systems. 410-413 - Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power trends and performance characterization of 3-dimensional integration. 414-417 - Qing K. Zhu, Michael Zhang:
Low-voltage swing clock distribution schemes. 418-421 - Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. 422-425 - Mohamed Nekili, Yvon Savaria, Guy Bois:
Minimizing process-induced skew using delay tuning. 426-429 - Luca Fanucci, Roberto Roncella, Roberto Saletti:
Non-linearity reduction technique for delay-locked delay-lines. 430-433 - Martin Makundi, Vesa Välimäki, Timo I. Laakso:
Closed-form design of tunable fractional-delay allpass filter structures. 434-437 - Shou-Sheu Lin, Wen-Rong Wu:
A low complexity adaptive interpolated FIR echo canceller. 438-441 - Liang C. Chu, Martin A. Brooke:
An enhancement study on the SDSL upstream receiver. 442-445 - Ming-Hwa Sheu, Ho-En Liao, Shih Tsung Kan, Ming-Der Shieh:
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. 446-449 - Thomas Magesacher, Per Ödling, Tomas Nordström, T. Lunberg, Mikael Isaksson, Per Ola Börjesson:
An adaptive mixed-signal narrowband interference canceller for wireline transmission systems. 450-453 - Alan N. L. Chan, Kenneth W. H. Ng, Joseph M. C. Wong, Howard C. Luong:
A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application. 454-457 - Risto Kaunisto, Petri Korpi, Jiri Kiraly, Kari Halonen:
A linear-control wide-band CMOS attenuator. 458-461 - Luca Fanucci, Giorgio D'Angelo, Andrea Monterastelli, Mario Paparo, Bruno Neri:
Fully integrated low-noise-amplifier with high quality factor L-C filter for 1.8 GHz wireless applications. 462-465 - J. C. Huang, Ro-Min Weng, Cheng-Chih Chang, Kang Hsu, Kun-Yi Lin:
A 2 V 2.4 GHz fully integrated CMOS LNA. 466-469 - Adiseno, Mohammed Ismail, Håkan K. Olsson:
Dual-loop cross-coupled feedback amplifier for low-IF integrated receiver architecture. 470-473 - Mohamed A. Elgamel, Ahmed M. Shams, Xi Xueling, Magdy A. Bayoumi:
Enhanced low power motion estimation VLSI architectures for video compression. 474-477 - Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen:
Interfacing multiple processors in a system-on-chip video encoder. 478-481 - Konstantina Karagianni, Thanos Stouraitis:
A vector processor for 3-D geometrical transformations. 482-485 - Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny:
A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. 486-489 - Piotr Dudek, Peter J. Hicks:
An analogue SIMD focal-plane processor array. 490-493 - Roberto Canegallo, Davide Dozza, Roberto Guerrieri:
Low power techniques for flash memories. 494-497 - Meenatchi Jagasivamani, Dong Sam Ha:
Development of a low-power SRAM compiler. 498-501 - William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria:
Fast system-level exploration of memory architectures driven by energy-delay metrics. 502-505 - Arnaud Turier, Lotfi Ben Ammar, Amara Amara:
Static power consumption management in CMOS memories. 506-509 - Byung-Do Yang, Lee-Sup Kim:
A low power charge-recycling ROM architecture. 510-513 - Kah-Howe Tan, Wen Fung-Leong, Sameer Kadam, Michael A. Soderstrand, Louis G. Johnson:
Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation. 514-517 - Li-Minn Ang, Hon Nin Cheung:
Hardware implementation of the depth first search bit stream SPIHT system. 518-521 - Ju Byoung Kim, Young Jin Lim, Moon Ho Lee:
A low complexity FEC design for DAB. 522-525 - Sergio L. Toral Marín, José M. Quero, Mar M. Elena Pérez, Leopoldo García Franquelo:
A microprocessor based system for ECG telemedicine and telecare. 526-529 - Kuan-Hung Chen, Shi-Chung Chang, Tzi-Dar Chiueh, Peter B. Luh, Xing Zhao:
SIMD architecture for job shop scheduling problem solving. 530-533 - Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu:
A hardware design approach for merge-sorting network. 534-537 - Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
A low power asynchronous DES. 538-541 - Chang-Ki Kwon, Kwyro Lee:
Reconfigurable and programmable minimum distance search engine for portable video compression systems. 542-545 - Kamal Rajagopalan, Peter R. Sutton:
A flexible multiplication unit for an FPGA logic block. 546-549 - Aiman H. El-Maleh, Yahya E. Osais:
A retiming-based test pattern generator design for built-in self test of data path architectures. 550-553 - Vijay K. Jain:
Hybrid wavelet/spread-spectrum system for broadband wireless LANs. 554-557 - Chien-Fang Hsu, Yuan-Hao Huang, Tzi-Dar Chiueh:
Design of an OFDM receiver for high-speed wireless LAN. 558-561 - A. Dhammika S. Jayalath, Chintha Tellambura:
Peak-to-average power ratio reduction of an OFDM signal using data permutation with embedded side information. 562-565 - Kanagaratnam Sathananthan, Chintha Tellambura:
Forward error correction codes to reduce intercarrier interference in OFDM. 566-569 - Jinwen Shentu, Jean Armstrong:
Blind frequency offset estimation for PCC-OFDM with symbols overlapped in the time domain. 570-573 - Lijun Gao, Keshab K. Parhi:
Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec. 574-577 - Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee:
New bit-parallel systolic multipliers for a class of GF(2m). 578-581 - Sung-Won Lee, In-Cheol Park:
A low-power variable length decoder based on successive decoding of shoft codewords. 582-585 - Mohammad K. Ibrahim, Abulaziz Almulhem:
Bit-level pipelined digit serial GF(2m) multiplier. 586-589 - Abdoul Rjoub, M. Alrousan, Omar M. Al-Jarrah, Odysseas G. Koufopavlou:
Multi-level low swing voltage values for low power design applications. 590-593 - Paul R. van der Meer, Arie van Staveren:
Effectivity of standby-energy reduction techniques for deep sub-micron CMOS. 594-597 - Takeo Yasuda, Masaaki Yamamoto, Takafumi Nishi:
A power-on reset pulse generator for low voltage applications. 599-601 - Rolf Becker:
Control loop for optimization of power consumption in VLSI designs. 602-605 - Byung G. Jo, Jin Y. Kang, Myung Hoon Sunwoo:
A low power and area efficient FIR filter chip for PRML read channels. 606-609 - Lai-Kan Leung, Cheong-Fat Chan, Oliver Chiu-sing Choy:
A giga-hertz CMOS digital controlled oscillator. 610-613 - Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung:
A low-power high driving ability voltage control oscillator used in PLL. 614-617 - Teemu Suutari, Jouni Isoaho, Hannu Tenhunen:
High-speed serial communication with error correction using 0.25 um CMOS technology. 618-621 - Ullas Singh, Michael Green:
New structures for very high-frequency CMOS clock dividers. 622-625 - Antti Heiskanen, Antti Mäntyniemi, Timo Rahkonen:
A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level. 626-629 - Rui L. Aguiar, Dinis M. Santos:
Oscillatorless clock multiplication. 630-633 - Hong-Yi Huang, Teng-Neng Wang:
High-speed CMOS logic circuits in capacitor coupling technique. 634-637 - Mauro Olivieri, Alessandro Trifiletti:
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores. 638-641 - Hamid Mahmoodi-Meimand, Ali Afzali-Kusha:
Efficient power clock generation for adiabatic logic. 642-645 - Natalia Kazakova, Raymond J. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux:
Fast and low-power inner product processor. 646-649 - Taek Won Kwon, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, Jun Rim Choi:
Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm. 650-653 - Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu:
Design of an efficient FFT processor for DAB system. 654-657 - Jiun-In Guo:
A low cost 2-D inverse discrete cosine transform design for image compression. 658-661 - Jiun-In Guo:
A new DA-based array for one dimensional discrete Hartley transform. 662-665 - Maw-Ching Lin, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou:
Low-power multiplierless FIR filter synthesizer based on CSD code. 666-669 - Chin-Liang Wang, Ching-Hsien Chang:
A new memory-based FFT processor for VDSL transceivers. 670-673 - Sherif Michael, Ronald J. Pieper:
A VLSI implementation of a universal programmable low sensitivity sampled data filter. 674-677 - Milena Stankovic, Radomir S. Stankovic, Jaakko Astola, Karen O. Egiazarian:
Circuit realization of spectral transforms in Fibonacci interconnection topologies. 678-681 - José M. Quintana, Maria J. Avedillo:
Reed-Muller descriptions of symmetric functions. 682-685 - José Luis Cura, Rui L. Aguiar:
Dynamic range boosting for wireless optical receivers. 686-689 - Kiyoshi Miyashita, Susumu Ichikawa, Yoshihiro Nakao, Naoto Shimataka, Takuji Otuki:
110 MHz IF-baseband CMOS receiver for J-CDMA/AMPS application. 690-693 - Jonghae Kim, Ramesh Harjani:
An ISM band CMOS integrated transceiver design for wireless telemetry system. 694-697 - Jaeyoung Shin, Joongho Choi, Jinup Lim, Sungwon Noh, Namil Baek, Jong-Hyeong Lee:
A 3.3-V analog front-end chip for HomePNA applications. 698-701 - Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo:
Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. 702-705 - Ping Wu, Kai He:
A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications. 706-709 - Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee:
A wideband digital frequency synthesizer. 710-713 - Pietro Andreani:
A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor. 714-717 - Ming-Ta Hsieh, Jackson Harvey, Ramesh Harjani:
Power optimization of CMOS LC VCOs. 718-721 - Robin R.-B. Sheen, Oscal T.-C. Chen:
A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz. 722-725 - Panu Hämäläinen, Marko Hännikäinen, Timo Hämäläinen, Henk Corporaal, Jukka Saarinen:
Implementation of encryption algorithms on transport triggered architectures. 726-729 - D. J. Soudris, Minas Dasygenis, Spyridoula K. Vasilopoulou, Adonios Thanailakis:
A CAD tool for architecture level exploration and automatic generation of RNS converters. 730-733 - Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa:
VLSI architecture of dynamically reconfigurable hardware-based cipher. 734-737 - Shoji Kawahito, Tatsuya Eki, Yoshiaki Tadokoro:
A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform. 738-741 - Chris J. Howland, Andrew J. Blanksby:
Parallel decoding architectures for low density parity check codes. 742-745 - Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. 746-749 - Edgar F. M. Albuquerque, Manuel M. Silva:
Evaluation of substrate noise in CMOS and low-noise logic cells. 750-753 - Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win:
ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. 754-757 - Ming-Dou Ker, Tung-Yang Chen:
Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. 758-761 - Imma Rovira, Pete Sivonen, Sami Rintamaki, Mauri Honkanen:
Highly linear TX IF-chip for multicarrier GSM 900 and 1800 base station. 762-765 - Adrian Maxim, Baker Scott, Ed Schneider, Melvin Hagge, Steve Chacko, Dan Stiurca:
Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. 766-769 - Kåre Tais Christensen:
Design and optimization of CMOS switches for switched tuning of LC resonators. 770-773 - José M. de la Rosa, Maria Belen Pérez-Verdú, Fernando Medeiro, Rocío del Río, Ángel Rodríguez-Vázquez:
Analysis and experimental characterization of idle tones in 2nd-order bandpass Sigma-Delta modulators-a 0.8 um CMOS switched-current case study. 774-777 - Kei-Tee Tiew, Alison J. Payne, Peter Y. K. Cheung:
MASH delta-sigma modulators for wideband and multi-standard applications. 778-781 - Cheng-Chih Chang, Ro-Min Weng, J. C. Huang, Kang Hsu, Kun-Yi Lin:
A 1.5 V high gain CMOS mixer for 2.4-GHz applications. 782-785 - Jackson Harvey, Ramesh Harjani:
Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection. 786-789 - Sami Karvonen, Tom A. D. Riley, Juha Kostamovaara:
A low noise quadrature subsampling mixer. 790-793 - Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng:
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage. 794-797 - Muhammad E. S. Elrabaa, Mohamed I. Elmasry:
Split-Gate Logic circuits for multi-threshold technologies. 798-801 - Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou:
A high-performance low-power static differential double edge-triggered flip-flop. 802-805 - Chulwoo Kim, Sung-Mo Kang:
A low-power reduced swing single clock flip-flop. 806-809 - Youcef Fouzar, Yvon Savaria, Mohamad Sawan:
A new controlled gain phase-locked loop technique. 810-813 - Ian Brynjolfson, Zeljko Zilic:
A new PLL design for clock management applications. 814-817 - Takayuki Hamamoto, Takeshi Wakamatsu, Kiyoharu Aizawa:
New method of on-sensor A/D conversion. 818-821 - Rachid Bouchakour, Nadia Harabech, Pierre Canet, Philippe Boivin, Jean Michel Mirable:
Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect. 822-825 - Huiyun Li, Bah-Hwee Gwee, Joseph Sylvester Chang:
A digital Class D amplifier design embodying a novel sampling process and pulse generator. 826-829 - Marco Ottavi, Gian Carlo Cardarilli, Panfilo Marinucci, Salvatore Pontarelli, Adelio Salsano:
Development of a dynamic routing system for a fault tolerant solid state mass memory. 830-833 - Ye Lu, Mourad N. El-Gamal:
A 2.3 V low noise, low power, 10 GHz bandwidth Si-bipolar transimpedance preamplifier for optical receiver front-ends. 834-837 - Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin:
Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. 838-841 - Tommy Kwong-Kin Tsang, Mourad N. El-Gamal:
A fully integrated 1 V 5.8 GHz bipolar LNA. 842-845 - Pierre Canet, Rachid Bouchakour, Nadia Harabech, Philippe Boivin, Jean-Michel Mirabel:
EEPROM programming study-time and degradation aspects. 846-849 - Somaya Ismail Kayed, Hani Fikry Ragaie, Mohamed Abou El-Ela, Fouad Abd Monem Soliman:
VLSI design and implementation of analog CMOS 2nd generation current conveyors. 850-853 - Yigang He, Yichuang Sun:
Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm. 854-857 - Takashi Ohira:
Emerging adaptive antenna techniques for wireless ad-hoc networks. 858-861 - Koichi Gyoda, Youiti Kado, Yuichiro Ohno, Kazuo Hasuike, Takashi Ohira:
WACNet - Wireless Ad-hoc Community Network. 862-865 - Tomoaki Ogawa, Eisuke Kudoh, Hirohito Suda:
Multi-routing schemes for ad-hoc wireless networks. 866-869 - Hongjun Xu, Kyung Sup Kwak:
Space-time block coding for wireless ad hoc networks. 870-873 - Hiroshi Tamura, Toshiyuhi Moriyama, Noriyoshi Matsumoto, Masakazu Sengoku, Kenichi Mase, Shoji Shinoda:
Routing algorithms on wireless multihop networks and their modifications. 874-877 - Yannick Dumonteix, Yann Bajot, Habib Mehrez:
A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic. 878-881 - Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic design with dual Vt. 882-885 - Rui Wang, Kaushik Roy, Cheng-Kok Koh:
Short-circuit power analysis of an inverter driving an RLC load. 886-889 - Alan N. L. Chan, Chun Bing Guo, Howard C. Luong:
A 1-V 2.4-GHz CMOS LNA with source degeneration as image-rejection notch filter. 890-893 - Kaoru Watanabe, Masakazu Sengoku, Hiroshi Tamura, Keisuke Nakano, Shoji Shinoda:
Graph problems in multi-hop networks. 894-897 - Kenichi Mase, Ritsuko Noto, Keisuke Nakano, Naoyuki Karasawa, Masakazu Sengoku, Shoji Shinoda:
A circuit-connection-based multihop wireless infrastructure for local communities. 898-901 - Jari Nikara, Jarmo Takala, David Akopian, Jukka Saarinen:
Pipeline architecture for DCT/IDCT. 902-905 - Minyi Fu, Vassil S. Dimitrov, Graham A. Jullien:
An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT. 906-909 - Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. 910-913 - Tay-Jyi Lin, Chein-Wei Jen:
An efficient 2-D DWT architecture via resource cycling. 914-917 - Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai:
An LSI for VDD-hopping and MPEG4 system based on the chip. 918-921 - Vasily G. Moshnyaga, Hiroshi Tsuji:
Cache energy reduction by dual voltage supply. 922-925 - Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen:
Power modeling and low-power design of content addressable memories. 926-929 - Toshihiko Yamasaki, Atsushi Suzuki, Daisuke Kobayashi, Tadashi Shibata:
A fast self-convergent flash-memory programming scheme for MV and analog data storage. 930-933 - Alessandro De Gloria, Mauro Olivieri:
An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors. 934-937 - Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures. 938-941
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