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2020 – today
- 2023
[c6]Yuta Aiba, Yusuke Higashi, Hitomi Tanaka, Hiroki Tanaka, Fumie Kikushima, Toshio Fujisawa, Hideko Mukaida, Masayuki Miura, Tomoya Sanuki:
Demonstration of Recovery Annealing on 7-Bits per Cell 3D Flash Memory at Cryogenic Operation for Bit Cost Scalability and Sustainability. VLSI Technology and Circuits 2023: 1-2- 2021
- [c5]Yuta Aiba, Hitomi Tanaka, Takashi Maeda, Keiichi Sawa, Fumie Kikushima, Masayuki Miura, Toshio Fujisawa, Mie Matsuo, Hideto Horii, Hideko Mukaida, Tomoya Sanuki:
Bringing in Cryogenics to Storage: Characteristics and Performance Improvement of 3D Flash Memory. IMW 2021: 1-4
2010 – 2019
- 2014
- [c4]Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda
, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki:
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. ISSCC 2014: 330-331 - 2011
- [j7]Tomoya Suzuki, Hideki Yamada, Toshiyuki Yamagishi, Daisuke Takeda, Koji Horisaki, Tom Vander Aa, Toshio Fujisawa, Liesbet Van der Perre, Yasuo Unekawa:
High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors. IEEE Micro 31(6): 19-28 (2011) - [c3]Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa:
A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. COOL Chips 2011: 1-3 - [c2]Hideki Yamada, Toshiyuki Yamagishi, Tomoya Suzuki, Kuniaki Ito, Koji Horisaki, Tom Vander Aa, Toshio Fujisawa, Liesbet Van der Perre, Yasuo Unekawa:
A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor. COOL Chips 2011: 1-3
2000 – 2009
- 2003
- [j6]Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa:
A single-chip 802.11a MAC/PHY with a 32-b RISC processor. IEEE J. Solid State Circuits 38(11): 2001-2009 (2003)
1990 – 1999
- 1992
- [j5]Toshinobu Kashiwabara, Sumio Masuda, Kazuo Nakajima, Toshio Fujisawa:
Generation of Maximum Independent Sets of a Bipartite Graph and Maximum Cliques of a Circular-Arc Graph. J. Algorithms 13(1): 161-174 (1992) - 1991
- [j4]Toshinobu Kashiwabara, Sumio Masuda, Kazuo Nakajima, Toshio Fujisawa:
Polynomial time algorithms on circular-arc overlap graphs. Networks 21(2): 195-203 (1991) - 1990
- [j3]Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa:
Efficient algorithms for finding maximum cliques of an overlap graph. Networks 20(2): 157-171 (1990) - [j2]Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa:
Crossing Minimization in Linear Embeddings of Graphs. IEEE Trans. Computers 39(1): 124-127 (1990)
1980 – 1989
- 1981
- [j1]Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa:
On Minimal Augmentation of a Graph to Obtain an Interval Graph. J. Comput. Syst. Sci. 22(1): 60-97 (1981)
1970 – 1979
- 1979
- [c1]Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa:
One-dimensional logic gate assignment and interval graphs. COMPSAC 1979: 101-106
Coauthor Index
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