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ORCIDHiroyuki Hara
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2010 – 2019
- 2016
[c14]Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC 2016: 132-133- 2015
- [c13]Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita:
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC 2015: 1-3 - 2013
- [j9]Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa:
A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation. IEICE Trans. Electron. 96-C(6): 894-902 (2013) - 2012
- [c12]Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa:
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. COOL Chips 2012: 1-3 - 2011
- [j8]Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki:
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. IEEE J. Solid State Circuits 46(1): 32-41 (2011) - [c11]Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe:
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. A-SSCC 2011: 161-164 - [c10]Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa:
A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. COOL Chips 2011: 1-3 - [c9]Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada:
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. ISSCC 2011: 338-340 - 2010
- [c8]Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki:
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC 2010: 326-327
2000 – 2009
- 2008
- [c7]Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada:
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. CICC 2008: 29-32 - [c6]Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi:
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC 2008: 262-263 - 2007
- [j7]Mutsumi Kimura, Shigeki Sawamura, Masakazu Kato, Yuji Hara, Daisuke Suzuki, Hiroyuki Hara, Satoshi Inoue:
Pulse-Width Modulation with Current Uniformization for TFT-OLEDs. IEICE Trans. Electron. 90-C(11): 2076-2082 (2007) - [c5]Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki:
An automated runtime power-gating scheme. ICCD 2007: 382-387 - 2006
- [j6]Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41(1): 54-62 (2006) - [j5]Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki:
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1379-1383 (2006) - [c4]Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami:
Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. ASP-DAC 2006: 533-540 - 2005
- [j4]Mutsumi Kimura, Yuji Hara, Hiroyuki Hara, Tomoyuki Okuyama, Satoshi Inoue, Tatsuya Shimoda:
Classification of Driving Methods for TFT-OLEDs and Novel Proposal Using Time Ratio Grayscale and Current Uniformization. IEICE Trans. Electron. 88-C(11): 2043-2050 (2005) - [c3]Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki:
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. CICC 2005: 527-530 - 2004
- [c2]Hiroyuki Hara, Mikio Sakurai, Mitsutoshi Miyasaka, Simon W. B. Tam, Satoshi Inoue, Tatsuya Shimoda:
Low temperature polycrystalline silicon TFT fingerprint sensor with integrated comparator circuit. ESSCIRC 2004: 403-406 - 2001
- [j3]Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda:
A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid State Circuits 36(5): 726-734 (2001)
1990 – 1999
- 1999
- [c1]Masahiro Umehira, Masamitsu Nakura, Makoto Umeuchi, Junichi Murayama, Takaaki Murai, Hiroyuki Hara:
Wireless and IP integrated system architectures for broadband mobile multimedia services. WCNC 1999: 593-597 - 1996
- [j2]Akilesh Parameswar, Hiroyuki Hara, Takayasu Sakurai:
A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. IEEE J. Solid State Circuits 31(6): 804-809 (1996) - 1994
- [j1]Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai:
A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. IEEE J. Solid State Circuits 29(12): 1482-1490 (1994)
Coauthor Index
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