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ORCIDIEEE Journal of Solid-State Circuits, Volume 36
Volume 36, Number 1, January 2001
- Gopal Raghavan, Joseph F. Jensen, J. Laskowski, Michael Kardos, Michael G. Case, Marko Sokolich, Stephen Thomas III:
Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators. 5-13 - Vincent Sin-Luen Cheung, Howard Cam Luong
, Wing-Hung Ki:
A 1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter. 14-22 - Thomas Hornak, Knud L. Knudsen, Andrew Z. Grzegorek, Ken A. Nishimura, William J. McFarland:
An image-rejecting mixer and vector filter with 55-dB image rejection over process, temperature, and transistor mismatch. 23-33 - Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka:
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. 34-39 - Albert Z. H. Wang, Chen-Hui Tsay:
An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology. 40-45 - Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara:
Design methodology of embedded DRAM with virtual-socket architecture. 46-54 - Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi:
Wordline voltage generating system for low-power low-voltage flash memories. 55-63 - Ralph Etienne-Cummings, Zaven Kevork Kalayjian, Donghui Cai:
A programmable focal-plane MIMD image processor chip. 64-73 - Peter H. Baechtold, Michael P. Beakes, Peter Buchmann, Rolf Clauberg, John F. Ewen, John F. Gilsdorf, Philippe Hauviller, Andreas Herkersdorf, Jean-Claude Le Garrec, Wolfram W. Lemppenau, Ben Parker, Dale J. Pearson, Joseph M. Pereira, Dominique Plassat, Scott K. Reynolds, Hans R. Schindler, André Steimle, David J. Webb, Albert X. Widmer:
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. 74-80 - Josep Altet, Antonio Rubio, Emmanuel Schaub, Stefan Dilhaire, Wilfrid Claeys:
Thermal coupling in integrated circuits: application to thermal testing. 81-91 - Hui Tian, Boyd Fowler, Abbas El Gamal:
Analysis of temporal noise in CMOS photodiode active pixel sensor. 92-101 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz:
An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers. 102-109 - Mike S. L. Lee, Bernard M. Tenbroek, William Redman-White, James Benson, Michael J. Uren:
A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation. 110-121 - Ming-Huang Liu, Shen-Iuan Liu:
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique. 122-128 - Mikko Waltari, Kari A. I. Halonen:
1-V 9-bit pipelined switched-opamp ADC. 129-134 - Po-Chiun Huang, Yi-Huei Chen, Chorng-Kuang Wang:
A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier. 135-138 - Nikolay T. Tchamov, Tero Niemi, Niko Mikkola:
High-performance differential VCO based on Armstrong oscillator topology. 139-141 - Paavo Väänänen, Mikko Metsänvirta, Nikolay T. Tchamov:
A 4.3-GHz VCO with 2-GHz tuning range and low phase noise. 142-146 - Bahram Fotouhi:
All-MOS voltage-to-current converter. 147-151 - Hao-Ping Hong, Jiin-Chuan Wu:
A reverse-voltage protection circuit for MOSFET power switches. 152-155 - Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, Chenming Hu:
Efficient generation of pre-silicon MOS model parameters for early circuit design. 156-159 - Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider:
Addition to "Digitally programmable switched-current FIR filter for low-voltage applications". 160
Volume 36, Number 2, February 2001
- Ravi Gupta, Brian M. Ballweber, David J. Allstot:
Design and optimization of CMOS RF power amplifiers. 166-175 - Pieter Rombouts, Wim De Wilde, Ludo Weyten:
A 13.5-b 1.2-V micropower extended counting A/D converter. 176-183 - Myung-Jun Choe, Bang-Sup Song, Kantilal Bacrania:
An 8-b 100-MSample/s CMOS pipelined folding ADC. 184-194 - Andrea Boni, Andrea Pierazzi, Carlo Morandi:
A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS. 195-203 - William S. T. Yan, Howard C. Luong:
A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers. 204-216 - Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, Marly Roncken:
An asynchronous instruction length decoder. 217-228 - Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee:
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. 229-238 - Yibin Ye, Kaushik Roy:
QSERL: quasi-static energy recovery logic. 239-248 - Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba:
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. 249-257 - Anders Edman, Jacob Christensen, Anders Emrich, Christer Svensson:
A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6-μm CMOS. 258-265 - Ching-Yuan Yang, Shen-Iuan Liu:
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques. 266-272 - Ganesh Balamurugan, Naresh R. Shanbhag:
The twin-transistor noise-tolerant dynamic circuit technique. 273-280 - Kimikazu Sano, Koichi Murata, Taiichi Otsuji, Tomoyuki Akeyoshi, Naofumi Shimizu, Eiichi Sano:
An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode. 281-289 - Ruchir Puri, Ching-Te Chuang, Mark B. Ketchen, Mario M. Pelella, Michael G. Rosenfield:
On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits. 290-298 - Dwight U. Thompson, Bruce A. Wooley:
A 15-b pipelined CMOS floating-point A/D converter. 299-303 - Chunyan Wang, M. Omair Ahmad, M. N. S. Swamy:
Design and implementation of a switched-current memory cell for low-power and weak-current operations. 304-307
Volume 36, Number 3, March 2001
- Lawrence E. Starr, Timothy T. Rueger:
Editorial. 312-314 - Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert, Willy Sansen:
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. 315-324 - Jonathan C. Jensen, Lawrence E. Larson:
A broadband 10-GHz track-and-hold in Si/SiGe HBT technology. 325-330 - Robert C. Taft, Maria Rosaria Tursi:
A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V. 331-338 - Eric Fogleman, Jared Welz, Ian Galton:
An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC. 339-348 - Mohamed Dessouky, Andreas Kaiser:
Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping. 349-355 - Patrick P. Siniscalchi, Jeanne K. Pitz, Richard K. Hester, Stewart M. DeSoto, Minsheng Wang, Sucheendran Sridharan, Robert L. Halbach, Donald Richardson, William Bright, Maher M. Sarraj, James R. Hellums, Christopher L. Betty, Glenn H. Westphal:
A CMOS ADSL codec for central office applications. 356-365 - Tai-Cheng Lee, Behzad Razavi:
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. 366-373 - Erich F. Haratsch, Kamran Azadet:
A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. 374-384 - Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz:
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. 385-397 - Kyung-Ho Cho, Henry Samueli:
A frequency-agile single-chip QAM modulator with beamforming diversity. 398-407 - Robert Pasko, Luc Rijnders, Patrick R. Schaumont, Serge A. Vernalde, Daniela Duracková:
High-performance flexible all-digital quadrature up and down converter chip. 408-416 - David J. Foley, Michael P. Flynn:
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator. 417-423 - Tsung-Hsien Lin, William J. Kaiser:
A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop. 424-431 - Seema Butala Anand, Behzad Razavi:
A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. 432-439 - Alexandre Vouilloz, Michel J. Declercq, Catherine Dehollain:
A low-power CMOS super-regenerative receiver at 1 GHz. 440-451 - Alain-Serge Porret, Thierry Melly, Dominique Python, Christian C. Enz, Eric A. Vittoz:
An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver. 452-466 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz:
An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter. 467-472 - Min Xu, David K. Su, Derek K. Shaeffer, Thomas H. Lee, Bruce A. Wooley:
Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver. 473-485 - Feng-Jung Huang, Kenneth K. O:
A 0.5-μm CMOS T/R switch for 900-MHz wireless applications. 486-492 - Hui Wu, Ali Hajimiri:
Silicon-based distributed voltage-controlled oscillators. 493-502 - Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba:
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. 503-509 - Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi:
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. 510-515 - Michele Borgatti, Alessandro Rocchi, Marco Bisio, Monica Besana, Loris Navoni, Pier Luigi Rolandi:
A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory. 516-521 - Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio:
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. 522-527 - Anne-Johan Annema, Govert J. G. M. Geelen, Peter C. de Jong:
5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. 528-538 - Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata:
Physical design guides for substrate noise reduction in CMOS digital circuits. 539-549 - Mohamed W. Allam, Mohamed I. Elmasry:
Dynamic current mode logic (DyCML): a new low-power high-performance logic style. 550-558 - Patrick Rakers, Larry Connell, Tim Collins, Dan Russell:
Secure contactless smartcard ASIC with DPA protection. 559-565 - Chris Binan Wang:
A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme. 566-569 - Dorin Emil Calbaza, Yvon Savaria:
Direct digital frequency synthesis of low-jitter clocks. 570-572
Volume 36, Number 4, April 2001
- Takayuki Hamamoto, Kiyoharu Aizawa:
A computational image sensor with adaptive pixel-based integration time. 580-585 - Markus Loose, Karlheinz Meier, Johannes Schemmel:
A self-calibrating single-chip CMOS camera with logarithmic response. 586-596 - Jente B. Kuang, David H. Allen, Ching-Te Chuang:
Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology. 597-604 - Tae-Sik Cheung, Bhum-Cheol Lee, Eun-Chang Choi, Woo-Young Choi:
A 1.8∼3.2-GHz fully differential GaAs MESFET PLL. 605-610 - Alfio Zanchi, Carlo Samori, Salvatore Levantino, Andrea L. Lacaita:
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. 611-619 - Alireza Zolfaghari, Andrew Chan, Behzad Razavi:
Stacked inductors and transformers in CMOS technology. 620-628 - Paolo Cusinato, Davide Tonietto, Fabrizio Stefani, Andrea Baschirotto:
A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulator with 74-dB dynamic range. 629-638 - Nicolas Kauffmann, Sylvain Blayac, Miloud Abboun, Philippe André, Frédéric Aniel, Muriel Riet, Jean-Louis Benchimol, Jean Godin, Agnieszka Konczykowska:
InP HBT driver circuit optimization for high-speed ETDM transmission. 639-647 - Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim:
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. 648-657 - Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl:
The impact of intrinsic device fluctuations on CMOS SRAM cell stability. 658-665 - Perng-Fei Lin, James B. Kuo:
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. 666-675 - Ming-Dou Ker, Tung-Yang Chen, Tai-Ho Wang, Chung-Yu Wu:
On-chip ESD protection design by using polysilicon diodes in CMOS process. 676-686 - Apisak Worapishet, John B. Hughes, Chris Toumazou:
Speed and accuracy enhancement techniques for high-performance switched-current comparators. 687-690 - Angus McLaren, Ken Martin:
Generation of accurate on-chip time constants and stable transconductances. 691-695 - Yasuhiro Sugimoto:
A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s. 696-700 - Ayman M. ElSayed, Mohamed I. Elmary:
Low-phase-noise LC quadrature VCO using coupled tank resonators in a ring structure. 701-705 - Andrea Boni, Andrea Pierazzi, Davide Vecchi:
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS. 706-711 - S. C. Liu, F. A. Wu, James B. Kuo:
A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. 712-716
Volume 36, Number 5, May 2001
- Stephen H. Lewis:
New associate editor. 723 - David B. Scott, Masakazu Yamashina:
Guest editorial. 724-725 - Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda:
A bitline leakage compensation scheme for low-voltage SRAMs. 726-734 - Kyehyun Kyung, Hi-Choon Lee, Ki-Whan Song, Ho-Sung Song, Keewook Jung, Joon-Seo Moon, Byoung-Sul Kim, Sung-Burn Cho, Changhyun Kim, Soo-In Cho:
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. 735-743 - Ken Takeuchi, Tomoharu Tanaka:
A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories. 744-751 - Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly:
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus. 752-760 - Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. 761-768 - Helen H. Kim, S. Chandrasekhar, Charles A. Burrus, Jon Bauman:
A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver. 769-776 - Chan-Hong Park, Ook Kim, Beomsup Kim:
A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching. 777-783 - Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho:
A dual-loop delay-locked loop using multiple voltage-controlled delay lines. 784-791 - Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie:
A clock distribution network for microprocessors. 792-799 - Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Wonchan Kim:
A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique. 800-809 - Behzad Razavi:
A 5.2-GHz CMOS receiver with 62-dB image rejection. 810-815 - Miguel E. Figueroa, David Hsu, Chris Diorio:
A mixed-signal approach to high-performance low-power linear filters. 816-822 - Changsik Yoo, Qiuting Huang:
A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS. 823-830 - Gerhard Knoblinger, Peter Klein, Marc Tiebout:
A new model for thermal channel noise of deep-submicron MOSFETs and its application in RF-CMOS design. 831-837 - Travis N. Blalock, Neela B. Gaddis, Ken A. Nishimura, Thomas A. Knotts:
True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction. 838-845 - Lisa G. McIlrath:
A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion. 846-853 - David S. Nack, Kenneth C. Dyer:
A constant slew rate Ethernet line driver. 854-858
Volume 36, Number 6, June 2001
- Ramesh Harjani:
A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process. 862-872 - Farbod Behbahani, Yoji Kishigami, John C. Leete, Asad A. Abidi:
CMOS mixers and polyphase filters for large image rejection. 873-887 - Osama Shana'a, Ivan Linscott, Len Tyler:
Frequency-scalable SiGe bipolar RF front-end design. 888-895 - Donhee Ham, Ali Hajimiri:
Concepts and methods in optimization of integrated LC VCOs. 896-909 - Lizhong Sun, Tadeusz Kwasniewski:
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator. 910-916 - Jing-Ling Yang, Chiu-Sing Choy, Cheong-Fat Chan:
A self-timed divider using a new fast and robust pipeline scheme. 917-923 - Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. 924-932 - Ming-Luen Lieu, Tzi-Dar Chiueh:
A low-power digital matched filter for direct-sequence spread-spectrum signal acquisition. 933-943 - Yong-Ha Park, Seon-Ho Han, Jung-Hwan Lee, Hoi-Jun Yoo:
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system. 944-955 - Hisatada Miyatake, Masahiro Tanaka, Yotaro Mori:
A design for high-speed low-power CMOS fully parallel content-addressable memory macros. 956-968 - Jorgo Tsouhlarakis, Guido Vanhorebeek, Geert Verhoeven, Jan De Blauwe, Shiho Kim, Dirk Wellekens, Paul Hendrickx, Luc Haspeslagh, Jan Van Houdt, Herman Maes:
A flash memory technology with quasi-virtual ground array for low-cost embedded applications. 969-978 - Andrea Boni:
1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS. 979-987 - Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka:
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. 988-996 - Hsin-Shu Chen, Bang-Sup Song, Kantilal Bacrania:
A 14-b 20-Msamples/s CMOS pipelined ADC. 997-1001
Volume 36, Number 7, July 2001
- Quiting Huang, Jos A. Huisken:
Guest editorial. 1008-1009 - Giuseppe Gramegna, Mario Paparo, Pietro G. Erratico, Placido De Vita:
A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA. 1010-1017 - Marc Tiebout:
Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS. 1018-1024 - Norbert Joehl, Catherine Dehollain, Patrick Favre, Philippe Deval, Michel J. Declercq:
A low-power 1-GHz super-regenerative transceiver with time-shared PLL control. 1025-1031 - Federico Bruccoleri, Eric A. M. Klumperink, Bram Nauta:
Generating all two-MOS-transistor amplifiers leads to new wide-band LNAs. 1032-1040 - Thomas Tille, Jens Sauerbrey, Doris Schmitt-Landsiedel:
A 1.8-V MOSFET-only ΣΔ modulator using substrate biased depletion-mode MOS capacitors in series compensation. 1041-1047 - Lauri Sumanen, Mikko Waltari, Kari A. I. Halonen:
A 10-bit 200-MS/s CMOS parallel pipeline A/D converter. 1048-1055 - Giacomino Bollati, Stefano Marchese, Marco Demicheli, Rinaldo Castello:
An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost. 1056-1066 - Dominique Python, Christian C. Enz:
A micropower class-AB CMOS log-domain filter for DECT applications. 1067-1075 - Piero Malcovati, Franco Maloberti, Carlo Fiocchi, Marcello Pruzzi:
Curvature-compensated BiCMOS bandgap with 1-V supply voltage. 1076-1081 - Torsten Lehmann, Marco Cassia:
1-V power supply CMOS cascode amplifier. 1082-1086 - Simona Brigati, Fabrizio Francesconi, Matteo Poletti, Daniela Fumagalli, Guido Grassi, Piero Malcovati:
A 147-dB dynamic range electronic attenuator for audiometric applications with on-chip 1-W power amplifier. 1087-1093 - K. Stangel, Stephan Kolnsberg, Dirk Hammerschmidt, Bedrich J. Hosticka, H. K. Trieu, W. Mokwa:
A programmable intraocular CMOS pressure sensor system implant. 1094-1100 - André Abrial, Jacky Bouvier, Marc Renaudin, Patrice Senn, Pascal Vivet:
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. 1101-1107 - Christer Svensson:
Optimum voltage swing on on-chip and off-chip interconnect. 1108-1112 - Patrik Larsson:
Measurements and analysis of PLL jitter caused by digital switching noise. 1113-1119 - Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya:
A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs. 1120-1126 - Axel Schmidt, Stéphane Catala:
A universal dual band LNA implementation in SiGe technology for wireless applications. 1127-1131 - Hans-Dieter Wohlmuth, Werner Simbürger:
A high-IP3 RF receiver chip set for mobile radio base stations up to 2 GHz. 1132-1137 - Gilbert Promitzer:
12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s. 1138-1143 - Mika P. Tiilikainen:
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC. 1144-1147 - Tuomas Hollman, Saska Lindfors, Mika Länsirinne, Jarkko Jussila, Kari A. I. Halonen:
A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA. 1148-1153 - Kyeong-Sik Min, Jin-Yong Chung:
A fast pump-down VBB generator for sub-1.5-V DRAMs. 1154-1157 - Raik Richter, Hans-Joachim Jentschel:
A virtual clock enhancement method for DDS using an analog delay line. 1158-1161
Volume 36, Number 8, August 2001
- Stephen H. Lewis:
Editorial. 1166 - Bernhard E. Boser:
Editorial. 1167 - Huanzhang Huang, Edward K. F. Lee:
Design of low-voltage CMOS continuous-time filter with on-chip automatic tuning. 1168-1177 - Yushi Shirato, Kiyoshi Kobayashi, Satoshi Denno:
100-Mbit/s single-chip Q-VLMS MLSE equalizer LSI for TDMA mobile radio communications. 1178-1185 - Kazuya Yamamoto, Tetsuya Heima, Akihiko Furukawa, Masayoshi Ono, Yasushi Hashizume, Hiroshi Komurasaki, Shigenobu Maeda, Hisayasu Sato, Naoyuki Kato:
A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch. 1186-1197 - Jussi Ryynänen, Kalle Kivekäs, Jarkko Jussila, Aarno Pärssinen, Kari A. I. Halonen:
A dual-band RF front-end for WCDMA and GSM applications. 1198-1204 - Farbod Behbahani, Ali Karimi-Sanjaani, Wee-Guan Tan, Andreas Roithmeier, John C. Leete, Koichi Hoshino, Asad A. Abidi:
Adaptive analog IF signal processor for a wide-band CMOS wireless receiver. 1205-1217 - Walter T. Bax, Miles A. Copeland:
A GMSK modulator using a ΔΣ frequency discriminator-based synthesizer. 1218-1227 - Tarmo Ruotsalainen, Pasi Palojärvi, Juha Kostamovaara:
A wide dynamic range receiver channel for a pulsed time-of-flight laser radar. 1228-1238 - Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Tin-Hao Lin:
Low switching noise and load-adaptive output buffer design techniques. 1239-1249 - Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh:
Analysis and design of high-speed and low-power CMOS PLAs. 1250-1262 - Bai-Sun Kong, Sam-Soo Kim, Young-Hyun Jun:
Conditional-capture flip-flop for statistical power reduction. 1263-1271 - Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan:
Asynchronous cross-pipelined multiplier. 1272-1275 - Jungho Lee, Joonbae Park, Byungjoon Song, Wonchan Kim:
Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic. 1276-1280 - Hideyuki Nosaka, Yo Yamaguchi, Akihiro Yamagishi, Hiroyuki Fukuyama, Masahiro Muraguchi:
A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique. 1281-1285 - Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata:
A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. 1286-1290
Volume 36, Number 9, September 2001
- Vincent M. Hietala, Carl Chun, Joy Laskar, Kent D. Choquette, Kent M. Geib, A. A. Allerman, J. J. Hindi:
Two-dimensional 8×8 photoreceiver array and VCSEL drivers for high-throughput optical data links. 1297-1302 - Hitoshi Ikeda, Tomoyuki Ohshima, Masanori Tsunotani, Toshihiko Ichioka, Tamotsu Kimura:
An auto-gain control transimpedance amplifier with low noise and wide input dynamic range for 10-Gb/s optical communication systems. 1303-1308 - Hisao Shigematsu, Masaru Sato, Toshihide Suzuki, Tsuyoshi Takahashi, Kenji Imanishi, Naoki Hara, Hiroaki Ohnishi, Yuu Watanaba:
A 49-GHz preamplifier with a transimpedance gain of 52 dBΩ using InP HEMTs. 1309-1313 - Hans Ransijn, Gregory Salvador, Dwight D. Daugherty, Kenneth D. Gaynor:
A 10-Gb/s laser/modulator driver IC with a dual-mode actively matched output buffer. 1314-1320 - Philippe André, Sylvain Blayac, Philippe Berdaguer, Jean-Louis Benchimol, Jean Godin, Nicolas Kauffmann, Agnieszka Konczykowska, Abed-Elhak Kasbari, Muriel Riet:
InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits. 1321-1327 - Marko Sokolich, Charles H. Fields, Stephen Thomas III, Binqiang Shi, Young Kim Boegeman, Mary Montes, Rosanna Martinez, Allan R. Kramer, Meena Madhav:
A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBT technology. 1328-1334 - Tom P. E. Broekaert, Willie Ng, Joseph F. Jensen, Daniel Yap, David L. Persechini, S. Bourgholtzer, Charles H. Fields, Young K. Brown-Boegeman, Binqiang Shi, Robert H. Walden:
InP-HBT optoelectronic integrated circuits for photonic analog-to-digital conversion. 1335-1342 - Shrinivasan Jaganathan, Sundararajan Krishnan, Dino Mensa, Thomas Mathew, Yoram Betser, Yun Wei, Dennis W. Scott, Miguel Urteaga, Mark J. W. Rodwell:
An 18-GHz continuous-time Σ-Δ analog-digital converter implemented in InP-transferred substrate HBT technology. 1343-1350 - Kenjiro Nishikawa, Kenji Kamogawa, Belinda Piernas, Masami Tokumitsu, Suehiro Sugitani, Ichihiko Toyoda, Katsuhiko Araki:
Three-dimensional MMIC technology for low-cost millimeter-wave MMICs. 1351-1359 - Sangwoo Han, Neeraj Lal, Chang-Ho Lee, Babak Matinpour, Joy Laskar:
Development of MMIC-based modules for multichannel RF/optical subcarrier multiplexed communications applications. 1360-1364 - Vassil Palankovski, Rüdiger Quay, Siegfried Selberherr:
Industrial application of heterostructure device simulation. 1365-1370 - Géraldine Bertrand, Christelle Delage, Marise Bafleur, Nicolas Nolhier, Jean-Marie Dorkel, Quang Nguyen, Nicolas Mauran, David Trémouilles, Philippe Perdu:
Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology. 1373-1381 - Rik Jos:
Technology developments driving an evolution of cellular phone power amplifiers to integrated RF front-end modules. 1382-1389 - Jeroen C. J. Paasschens, Willy J. Kloosterman, Ramon J. Havens, Henk C. de Graaff:
Improved compact modeling of output conductance and cutoff frequency of bipolar transistors. 1390-1398 - Wibo D. van Noort, Leo C. N. de Vreede, H. F. F. Jos, Lis K. Nanver, Jan W. Slotboom:
Reduction of UHF power transistor distortion with a nonuniform collector doping profile. 1399-1406 - Wolfgang Thomann, Josef Fenk, Richard Hagelauer, Robert Weigel:
Fully integrated W-CDMA IF receiver and IF transmitter including IF synthesizer and on-chip VCO for UMTS mobiles. 1407-1419 - Herbert Knapp, Josef Böck, Martin Wurzer, Günter Ritzberger, Klaus Aufinger, Ludwig Treitinger:
2-GHz/2-mW and 12-GHz/30-mW dual-modulus prescalers in silicon bipolar technology. 1420-1423 - Guofu Niu, Zhenrong Jin, John D. Cressler, Rao Rapeta, Alvin J. Joseph, David L. Harame:
Transistor noise in SiGe HBT RF technology. 1424-1427
Volume 36, Number 10, October 2001
- Eyad Abou-Allam, John J. Nisbet, Michael C. Maliepaard:
Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology. 1434-1443 - Francesco Gatta, Enrico Sacchi, Francesco Svelto, Paolo Vilmercati, Rinaldo Castello:
A 2-dB noise figure 900-MHz differential CMOS LNA. 1444-1452 - Chang-Hyeon Lee, Kelly McClellan, John Choma Jr.:
A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter. 1453-1463 - Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu:
A fast-lock mixed-mode DLL using a 2-b SAR algorithm. 1464-1471 - Yu-Lung Tang, Huei Wang:
Triple-push oscillator approach: theory and experiments. 1472-1479 - Bendik Kleveland, Carlos H. Diaz, Dieter Vook, Liam Madden, Thomas H. Lee, S. Simon Wong:
Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design. 1480-1488 - Jun Ming, Stephen H. Lewis:
An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration. 1489-1497 - Wei-Hung Chen, Guang-Kaai Dehang, Jong-Woei Chen, Shen-Iuan Liu:
A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme. 1498-1505 - Bharadwaj S. Amrutur, Mark A. Horowitz:
Fast low-power decoders for RAMs. 1506-1515 - Ching-Rong Chang, Jinn-Shyan Wang, Cheng-Hui Yang:
Low-power and high-speed ROM modules for ASIC applications. 1516-1523 - Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine:
A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. 1524-1537 - Yun Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig:
A carry-free 54b×54b multiplier using equivalent bit conversion algorithm. 1538-1545 - Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino:
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. 1546-1552 - Yevgeny Perelman, Ran Ginosar:
A low-light-level sensor for medical diagnostic applications. 1553-1558 - Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai:
Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. 1559-1564 - Alper Ilkbahar, Srinivas Venkataraman, Harry Muljono:
ItaniumTM Processor system bus design. 1565-1573 - In-Chul Hwang, Sang-Hun Song, Soo-Won Kim:
A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition. 1574-1581 - Chien-Hung Kuo, Shr-Lung Chen, Lee-An Ho, Shen-Iuan Liu:
CMOS oversampling ΔΣ magnetic-to-digital converters. 1582-1586 - Takashi Sato, Dennis Sylvester, Yu Cao, Chenming Hu:
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling. 1587-1591 - Qiang Zhang, Juin J. Liou, John McMacken, J. Ross Thomson, Paul Layman:
SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests. 1592-1595
Volume 36, Number 11, November 2001
- Lawrence T. Clark, Eric J. Hoffman, Jay B. Miller, Manish Biyani, Yuyun Liao, Stephen J. Strazdus, Michael Morrow, Kimberley E. Velarde, Mark A. Yarch:
An embedded 32-b microprocessor core for low-power and high-performance applications. 1599-1608 - Andre Kowalczyk, Victor Adler, Chaim Amir, Frank Chiu, Choon Ping Chng, Willem J. de Lange, Yuefei Ge, Subhendra Ghosh, Tan Canh Hoang, Baoqing Huang, Shree Kant, Y. S. Kao, Cong Khieu, Suresh Kumar, Lan Lee, Avi Liebermensch, Xin Liu, Naveen G. Malur, Albert A. Martin, Hiep Ngo, Sung-Hun Oh, Ioannis Orginos, Lorraine Shih, Balmiki Sur, Marc Tremblay, Allan Tzeng, Dan Vo, Sanjay Zambare, Jin Zong:
The first MAJC microprocessor: a dual CPU system-on-a-chip. 1609-1616 - Glenn Hinton, Michael Upton, David J. Sager, Darrell Boggs, Douglas M. Carmean, Patrice Roussel, Terry I. Chappell, Thomas D. Fletcher, Mark S. Milshtein, Milo Sprague, Samie Samaan, Robert Murray:
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit. 1617-1627 - Jens Leenstra, Jürgen Pille, Antje Müller, Wolfram M. Sauer, Rolf Sautter, Dieter F. Wendel:
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. 1628-1635 - Sanu K. Mathew, Ram K. Krishnamurthy, Mark A. Anders, Rafael Rios, Kaizad R. Mistry, Krishnamurthy Soumyanath:
Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends. 1636-1646 - Nasser A. Kurd, Javed S. Barkatullah, Rommel O. Dizon, Thomas D. Fletcher, Paul D. Madland:
A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor. 1647-1653 - John Wood, Terence C. Edwards, Steve Lipa:
Rotary traveling-wave oscillator arrays: a new clock technology. 1654-1665 - Kouichi Yamaguchi, Muneo Fukaishi, Takehiko Sakamoto, Naoto Akiyama, Kazuyuki Nakamura:
A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture. 1666-1672 - Adrian Maxim, Baker Scott, Edmund M. Schneider, Melvin Hagge, Steve Chacko, Dan Stiurca:
A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter. 1673-1683 - Chih-Kong Ken Yang, Vladimir Stojanovic, Siamak Modjtahedi, Mark A. Horowitz, William F. Ellersick:
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS. 1684-1692 - Joseph M. Ingino, Vincent R. von Kaenel:
A 4-GHz clock system for a high-performance system-on-a-chip design. 1693-1698 - Taehee Cho, Yeong-Taek Lee, Eun-Cheol Kim, Jin-Wook Lee, Sunmi Choi, Seungjae Lee, Dong-Hwan Kim, Wook-Ghee Han, Young-Ho Lim, Jae-Duk Lee, Jung-Dal Choi, Kang-Deog Suh:
A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes. 1700-1706 - Tatsuya Ishii, Kazuyoshi Oshima, Hiroshi Sato, Satoshi Noda, Jiro Kishimoto, Hiroaki Kotani, Atsushi Nozoe, Kazunori Furusawa, Takayuki Yoshitake, Masataka Kato, Masahito Takahashi, Akihiko Sato, Shoji Kubono, Kiichi Manita, Kenji Koda, Takeshi Nakayama, Akira Hosogane:
A 126.6-mm2 AND-type 512-Mb flash memory with 1.8-V power supply. 1707-1712 - Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki:
A 76-mm2 8-Mb chain ferroelectric memory. 1713-1720 - Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh:
A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. 1721-1727 - Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi:
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. 1728-1737 - Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi:
Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. 1738-1744 - Bernhard Wicht, Steffen Paul, Doris Schmitt-Landsiedel:
Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers. 1745-1755 - Chi Weon Yoon, Ramchan Woo, Jeengheon Kook, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yeo:
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications. 1758-1767 - Tatsuya Koyama, Keisuke Inoue, Hirokazu Hanaki, Masahiro Yasue, Eiji Iwata:
A 250-MHz single-chip multiprocessor for audio and video signal processing. 1768-1774 - Aurangzeb K. Khan, Hidetaka Magoshi, Tadashi Matsumoto, Jun-Ichi Fujita, Makoto Furuhashi, Masatoshi Imai, Yoshikazu Kurose, Morio Sato, Katsuhiko Sato, Yujiro Yamashita, Kinying Kwan, Duc-Ngoc Le, John H. Yu, Trung Nguyen, Steven Yang, Allen Tsou, King Chow, John Shen, Min Li, Jun Li, Hong Zhao, Kenji Yoshida:
A 150-MHz graphics rendering processor with 256-Mb embedded DRAM. 1775-1784 - Takashi Yamamoto, Shin-Ichi Gotoh, Toshihiko Takahashi, Kozo Irie, Kazuya Ohshima, Nobuhiro Mimura, Kazutoshi Aida, Toshinori Maeda, Koji Sushihara, Yoichi Okamoto, Yasuhiro Tai, Makoto Usui, Takeshi Nakajima, Takahiro Ochi, Katsuhiko Komichi, Akira Matsuzawa:
A mixed-signal 0.18-μm CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM. 1785-1794 - Derrick Chunkai Wei, Daniel Qicheng Sun, Asad A. Abidi:
A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive read channel. 1795-1807 - James Goodman, Anantha P. Chandrakasan:
An energy-efficient reconfigurable public-key cryptography processor. 1808-1820 - Eugene Grayver, Babak Daneshrad:
VLSI implementation of a 100-μW multirate FSK receiver. 1821-1828 - Wolfgang Eberle, Veerle Derudder, Geert Vanwijnsberghe, Mario Vergara, Luc Deneire, Liesbet Van der Perre, Marc Engels, Ivo Bolsens, Hugo De Man:
80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band. 1829-1838
Volume 36, Number 12, December 2001
- Michael Choi, Asad A. Abidi:
A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS. 1847-1858 - Hendrik van der Ploeg, Gian Hoogzaad, Henk A. H. Termeer, Maarten Vertregt, Raf L. J. Roovers:
A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration. 1859-1867 - Thomas Burger, Qiuting Huang:
A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSM dual-standard IF reception. 1868-1878 - Lucien J. Breems, Eise Carel Dijkmans, Johan H. Huijsing:
A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator. 1879-1886 - Katelijn Vleugels, Shahriar Rabii, Bruce A. Wooley:
A 2.5-V sigma-delta modulator for broadband communications applications. 1887-1899 - Kush Gulati, Hae-Seung Lee:
A low-power reconfigurable analog-to-digital converter. 1900-1911 - Nagendra Krishnapura, Yannis P. Tsividis:
Noise and power reduction in filters through the use of adjustable biasing. 1912-1920 - Emad Hegazi, Henrik Sjöland, Asad A. Abidi:
A filtering technique to lower LC oscillator phase noise. 1921-1930 - Wenhua William Yang, Dan Kelly, Iuri Mehr, Mark T. Sayuk, Larry Singer:
A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. 1931-1936 - Mario Reinhold, Claus Dorschky, Eduard Rose, Rajasekhar Pullela, Peter Mayer, Frank Kunz, Yves Baeyens, Thomas Link, John Paul Mattia:
A fully integrated 40-Gb/s clock and data recovery IC with 1: 4 DEMUX in SiGe technology. 1937-1945 - Hong-Ih Cong, Shawn M. Logan, Marc J. Loinaz, Kenneth J. O'Brien, Elizabeth E. Perry, Gary D. Polhemus, John E. Scoggins, Kenneth P. Snowdon, Michael G. Ward:
A 10-Gb/s 16: 1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS. 1946-1953 - Howard Wilson, Matthew Haycock:
A six-port 30-GB/s nonblocking router component using point-to-point simultaneous bidirectional signaling for high-bandwidth interconnects. 1954-1963 - Afshin Momtaz, Jun Cao, Mario Caresosa, Armond Hairapetian, David Chung, Kambiz Vakilian, Michael M. Green, Wee-Guan Tan, Keh-Chee Jen, Ichiro Fujimori, Yijun Cai:
A fully integrated SONET OC-48 transceiver in standard CMOS. 1964-1973 - Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn:
A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. 1974-1983 - Takeshi Nagahori, Kazunori Miyoshi, Yukio Aizawa, Yuki Kusachi, Yasuaki Nukada, Nobuharu Kami, Naofumi Suzuki:
An analog front-end chip set employing an electro-optical mixed design on SPICE for 5-Gb/s/ch parallel optical interconnection. 1984-1991 - Shahrzad Tadjpour, Ellie Cijvat, Emad Hegazi, Asad A. Abidi:
A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS. 1992-2002 - Jeffrey A. Weldon, R. Sekhar Narayanaswami, Jacques Christophe Rudell, Li Lin, Masanori Otsuka, Sébastien Dedieu, Luns Tee, King-Chun Tsai, Cheol-Woong Lee, Paul R. Gray:
A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers. 2003-2015 - Hooman Darabi, Shahla Khorram, Hung-Ming (Ed) Chien, Meng-An Pan, Stephen Wu, Shervin Moloudi, John C. Leete, Jacob J. Rael, Masood Syed, Robert Lee, Brima Ibrahim, Maryam Rofougaran, Ahmadreza Rofougaran:
A 2.4-GHz CMOS transceiver for Bluetooth. 2016-2024 - Jarkko Jussila, Jussi Ryynänen, Kalle Kivekäs, Lauri Sumanen, Aarno Pärssinen, Kari A. I. Halonen:
A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA. 2025-2029 - Erik Lauwers, Jan Suls, Walter Gumbrecht, David Maes, Georges G. E. Gielen, Willy Sansen:
A CMOS multiparameter biochemical microsensor with temperature control and signal interfacing. 2030-2038 - Jan Doutreloigne, Herbert De Smet, André Van Calster:
A versatile micropower high-voltage flat-panel display driver in a 100-V 0.7-μm CMOS intelligent interface technology. 2039-2048 - Stuart Kleinfelder, Sukhwan Lim, Xinqiao Liu, Abbas El Gamal:
A 10000 frames/s CMOS digital pixel sensor. 2049-2059
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