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ORCIDFlorentin Dartu
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2010 – 2019
- 2013
[c18]Florentin Dartu, Qiuyang Wu:
To do or not to do hierarchical timing? ISPD 2013: 180- 2010
- [j4]Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy:
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 497-502 (2010)
2000 – 2009
- 2006
- [c17]Kenneth S. Stevens, Florentin Dartu:
Algorithms for MIS vector generation and pruning. ICCAD 2006: 408-414 - 2005
- [j3]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Weibull-based analytical waveform model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1156-1168 (2005) - [c16]Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail:
Statistical static timing analysis: how simple can we get? DAC 2005: 652-657 - [c15]Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu:
Piece-wise approximations of RLCK circuit responses using moment matching. DAC 2005: 927-932 - [c14]Florentin Dartu, Anirudh Devgan, Noel Menezes:
Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 1 - [c13]Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Expanding the frequency range of AWE via time shifting. ICCAD 2005: 935-938 - 2004
- [c12]Aseem Agarwal, Florentin Dartu, David T. Blaauw:
Statistical gate delay model considering multiple input switching. DAC 2004: 658-663 - [c11]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Modeling unbuffered latches for timing analysis. ICCAD 2004: 254-260 - 2003
- [c10]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Weibull Based Analytical Waveform Model. ICCAD 2003: 161-168 - 2002
- [j2]Emrah Acar, Florentin Dartu, Lawrence T. Pileggi:
TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 605-616 (2002) - [c9]Seung Hoon Choi, Kaushik Roy, Florentin Dartu:
Timed pattern generation for noise-on-delay calculation. DAC 2002: 870-873
1990 – 1999
- 1998
- [c8]Florentin Dartu, Lawrence T. Pileggi:
TETA: Transistor-Level Engine for Timing Analysis. DAC 1998: 595-598 - 1997
- [c7]Florentin Dartu, Lawrence T. Pileggi:
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC 1997: 46-51 - [c6]Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi:
CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229 - 1996
- [j1]Florentin Dartu, Noel Menezes, Lawrence T. Pileggi:
Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 544-553 (1996) - [c5]Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi:
RC-Interconnect Macromodels for Timing Simulation. DAC 1996: 544-547 - [c4]Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi:
An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC 1996: 611-616 - 1994
- [c3]Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage:
A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580 - [c2]Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage:
RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425 - 1993
- [c1]Ion Constatin Tesu, Florentin Dartu:
Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits. ISCAS 1993: 1718-1721
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