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ORCIDVikas Rana
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2020 – today
- 2024
[c41]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC 2024: 282-287- [c40]Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. ETS 2024: 1-4 - [c39]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. VLSI-SoC 2024: 1-6 - [c38]Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker
, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay:
Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG. VLSID 2024: 560-564 - [c37]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID 2024: 565-570 - [i9]Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn:
Error Detection and Correction Codes for Safe In-Memory Computations. CoRR abs/2404.09818 (2024) - [i8]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. CoRR abs/2407.02921 (2024) - [i7]Chandan Singh, Vasileios G. Ntinas, Dimitrios A. Prousalis, Yongmin Wang, Ahmet Samil Demirkol, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff:
Employing Vector Field Techniques on the Analysis of Memristor Cellular Nonlinear Networks Cell Dynamics. CoRR abs/2408.03260 (2024) - 2023
- [j6]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15(4): 230-233 (2023) - [j5]Seokki Son, Camilla La Torre, Andreas Kindsmüller, Vikas Rana, Stephan Menzel:
A Study of the Electroforming Process in 1T1R Memory Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 558-568 (2023) - [c36]Vasileios G. Ntinas, Yongmin Wang, Ahmet Samil Demirkol, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff:
Design and Analysis of Isolated Voltage-Mode Memristor Cellular Nonlinear Network Cells. ISCAS 2023: 1-5 - [c35]Nicolas Schmitt, Alon Ascoli, Ioannis Messaris, Ahmet Samil Demirkol, Vasileios G. Ntinas, Dimitrios A. Prousalis, Ronald Tetzlaff, Spyridon Nikolaidis, Stephan Menzel, Vikas Rana:
Exploration of Bistable Oscillatory Dynamics in a Memristor from Forschungszentrum Jülich. MOCAST 2023: 1-6 - [c34]Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant:
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. NANOARCH 2023: 30:1-30:7 - [c33]Yongmin Wang, Kristoffer Schnieders, Vasileios G. Ntinas, Alon Ascoli, Felix Cüppers, Susanne Hoffmann-Eifert, Stefan Wiefels, Ronald Tetzlaff, Vikas Rana, Stephan Menzel:
Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task. NANOARCH 2023: 36:1-36:7 - [c32]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS 2023: 1-5 - [c31]Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant:
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. NEWCAS 2023: 1-5 - [c30]Vasileios G. Ntinas, Dharmik Patel, Yongmin Wang, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff:
A Simplified Variability-Aware VCM Memristor Model for Efficient Circuit Simulation. SMACD 2023: 1-4 - [c29]Gokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay:
PR-PUF: A Reconfigurable Strong RRAM PUF. VLSI-SoC 2023: 1-6 - [i6]Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant:
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. CoRR abs/2304.13531 (2023) - [i5]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR abs/2304.13552 (2023) - [i4]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR abs/2307.03669 (2023) - [i3]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR abs/2309.04868 (2023) - [i2]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR abs/2310.10460 (2023) - 2022
- [j4]Vasileios G. Ntinas, Alon Ascoli, Ioannis Messaris, Yongmin Wang, Vikas Rana, Stephan Menzel, Ronald Tetzlaff:
Toward Simplified Physics-Based Memristor Modeling of Valence Change Mechanism Devices. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2473-2477 (2022) - [c28]Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krüger, Letícia Maria Bolzani Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max Christian Lemme, Rainer Leupers, Rainer Waser:
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE 2022: 957-962 - [c27]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE 2022: 1181-1184 - [c26]Yongmin Wang, Alon Ascoli, Ronald Tetzlaff, Vikas Rana, Stephan Menzel:
Performance Analysis of Memristive-CNN based on a VCM Device Model. ISCAS 2022: 1184-1188 - [c25]Christopher Bengel, Stefan Wiefels, Vikas Rana, Hsin-Yu Chen, Qing-Tai Zhao, Rainer Waser, Henriette Padberg, Fengben Xi, Stephan Menzel:
Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory. ISCAS 2022: 2792-2796 - 2021
- [c24]Vikas Rana, Teddy Le Nguyen, Veera Raghava, Prahlad G. Menon:
Intelligent patient monitoring for proactive alerting of key personnel in intensive care: A single-center study. EMBC 2021: 2083-2086 - [c23]Alon Ascoli, Ronald Tetzlaff, Stephan Menzel, Vikas Rana:
System Theory Enables a Deep Exploration of ReRAM Cells' Switching Phenomena. ICECS 2021: 1-6 - [c22]Tim Kempen, Rainer Waser, Vikas Rana:
50x Endurance Improvement in TaOx RRAM by Extrinsic Doping. IMW 2021: 1-4 - [c21]Christopher Bengel, Anne Siemon, Vikas Rana, Stephan Menzel:
Implementation of Multinary Łukasiewicz Logic Using Memristive Devices. ISCAS 2021: 1-5 - [c20]Wonjoo Kim, Dirk J. Wouters, Rainer Waser, Vikas Rana:
Tuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power. ISCAS 2021: 1-5 - [c19]Vivek Tyagi, Shivam Kalla, Vikas Rana:
Negative Voltage Generator and Current DAC Based Regulator For Flash Memory. VLSID 2021: 17-22 - [c18]Vivek Tyagi, Vikas Rana:
Adaptive Forward Body Bias Voltage Generator. VLSID 2021: 23-28 - [i1]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR abs/2112.01087 (2021) - 2020
- [c17]Camilla La Torre, Andreas Kindsmüller, Seokki Son, Rainer Waser, Vikas Rana, Stephan Menzel:
A Compact Model for the Electroforming Process of Memristive Devices. ECCTD 2020: 1-4 - [c16]Prakhar Shukla, Prabhat Singh, Tushar Maheshwari, Anuj Grover, Vikas Rana:
A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP. ICECS 2020: 1-4 - [c15]Vikas Rana, Shivam Kalla:
Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency. SoCC 2020: 129-134 - [c14]Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti:
Power Efficient Sense Amplifier For Emerging Non Volatile Memories. VLSID 2020: 7-12
2010 – 2019
- 2019
- [c13]Marcella Carissimi, Ritesh Mukherjee, Vivek Tyagi, Fabio Disegni, Davide Manfrè, Cesare Torti, Daniele Gallinari, Sandro Rossi, Andrea Gambero, Donatella Brambilla, Paola Zuliani, Riccardo Zurla, Alessandro Cabrini, Guido Torelli, Marco Pasotti, Chantal Auricchio, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Stefano Zanchi, Vikas Rana, Preeti Mishra:
2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications. ESSCIRC 2019: 135-138 - [c12]Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Riccardo Zurla, Marco Pasotti:
Current DAC Based -40dB PSRR Configurable Output LDO in BCD Technology. VLSID 2019: 317-322 - 2018
- [j3]Marco Pasotti, Riccardo Zurla, Marcella Carissimi, Chantal Auricchio, Donatella Brambilla, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Daniele Gallinari, Cristina Mazzaglia, Vikas Rana, Alessandro Cabrini, Guido Torelli:
A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications. IEEE J. Solid State Circuits 53(7): 2114-2125 (2018) - [j2]Vikas Rana, Marco Pasotti, Marcella Carissimi:
Row decoder for embedded Phase Change Memory using low voltage transistors. Microelectron. J. 81: 117-122 (2018) - [j1]Vikas Rana, Rohan Sinha:
Stress Relaxed Multiple Output High-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 65-II(2): 176-180 (2018) - [c11]Vikas Rana:
Switched Capacitor based Area Efficient Positive and Negative Voltage Multiplier. APCCAS 2018: 74-77 - [c10]Vikas Rana, Abhishek Mittal:
Switched Capacitor based High Positive and Negative Voltage Charge-pump using Sample and Hold technique. APCCAS 2018: 78-81 - [c9]Vikas Rana:
Area Efficient NMOS Based Positive and Negative Voltage Multiplier. ISVLSI 2018: 10-15 - [c8]Vikas Rana:
CMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation. VLSID 2018: 181-185 - 2017
- [c7]Marco Pasotti, Marcella Carissimi, Chantal Auricchio, Donatella Brambilla, Emanuela Calvetti, Laura Capecchi, Luigi Croce, Daniele Gallinari, Cristina Mazzaglia, Vikas Rana, Riccardo Zurla, Alessandro Cabrini, Guido Torelli:
A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications. ESSCIRC 2017: 320-323 - [c6]Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana:
A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator. VDAT 2017: 144-152 - [c5]Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana:
A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM. VDAT 2017: 631-645 - [c4]Vikas Rana, Marco Pasotti, F. Desantis:
Single charge-pump generating high positive and negative voltages driving common load. VLSI-SoC 2017: 1-6 - 2016
- [c3]Wonjoo Kim, Dirk J. Wouters, Stephan Menzel, Christian Rodenbucher, Rainer Waser, Vikas Rana:
Lowering forming voltage and forming-free behavior of Ta2O5 ReRAM devices. ESSDERC 2016: 164-167 - [c2]Amit Chhabra, Vikas Rana:
-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI. VLSID 2016: 179-184 - 2012
- [c1]Rainer Waser, Stephan Menzel, Vikas Rana:
Recent progress in redox-based resistive switching. ISCAS 2012: 1596-1599
Coauthor Index
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