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Takumi Fujimori
Person information
- affiliation: Shizuoka University, Japan
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2020 – today
- 2023
- [c13]Takumi Fujimori
, Shuou Nomura
:
BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency. SYSTOR 2023: 94-104
2010 – 2019
- 2018
- [c12]Takumi Fujimori, Minoru Watanabe:
A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory. AHS 2018: 218-224 - [c11]Takumi Fujimori, Minoru Watanabe:
High total-ionizing-dose tolerance field programmable gate array. ISCAS 2018: 1-4 - 2017
- [c10]Takumi Fujimori, Minoru Watanabe:
Holographic Memory Calculation FPGA Accelerator for Optically Reconfigurable Gate Arrays. DASC/PiCom/DataCom/CyberSciTech 2017: 620-625 - [c9]Takumi Fujimori, Minoru Watanabe:
Multi-context scrubbing method. MWSCAS 2017: 1548-1551 - [c8]Takumi Fujimori, Minoru Watanabe:
Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array. SoCC 2017: 91-95 - 2016
- [c7]Takumi Fujimori, Minoru Watanabe:
Full FPGA game machine. ICCE 2016: 431-432 - 2015
- [c6]Minoru Watanabe, Takumi Fujimori:
Holographic scrubbing technique for a programmable gate array. AHS 2015: 1-5 - [c5]Takumi Fujimori, Minoru Watanabe:
Parallel-Operation-Oriented Optically Reconfigurable Gate Array. ARCS 2015: 3-14 - [c4]Takumi Fujimori, Tomoya Akabe
, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe:
FPGA Trax Solver based on a neural network design. FPT 2015: 260-263 - 2014
- [c3]Takumi Fujimori, Minoru Watanabe:
Radiation Tolerance of Color Configuration on an Optically Reconfigurable Gate Array. IPDPS Workshops 2014: 205-210 - 2013
- [c2]Takumi Fujimori, Minoru Watanabe:
Color configuration method for an optically reconfigurable gate array. FPT 2013: 406-409 - [c1]Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe:
FPGA Blokus Duo Solver using a massively parallel architecture. FPT 2013: 494-497
Coauthor Index
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