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ORCIDSinan Kaptanoglu
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2010 – 2019
- 2011
[c9]Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner:
A 65nm flash-based FPGA fabric optimized for low cost and power. FPGA 2011: 87-96
2000 – 2009
- 2008
- [j2]Wenyi Feng, Sinan Kaptanoglu:
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy. ACM Trans. Reconfigurable Technol. Syst. 1(1): 6:1-6:28 (2008) - 2007
- [c8]Wenyi Feng, Sinan Kaptanoglu:
Designing efficient input interconnect blocks for LUT clusters using counting and entropy. FPGA 2007: 23-32 - [c7]Sinan Kaptanoglu:
Power and the Future FPGA Architectures. FPT 2007 - 2004
- [c6]Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini:
Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144 - 2003
- [c5]Sinan Kaptanoglu:
System LSI Implementation Fabrics for the Future (special panel discussion). ICCD 2003: 410- - 2001
- [c4]Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta:
Is marriage in the cards for programmable logic, microprocessors and ASICs? FPGA 2001: 111
1990 – 1999
- 1999
- [c3]Sinan Kaptanoglu, Greg Bakker, Arun Kundu, Ivan Corneillet, Ben Ting:
A New High Density and Very Low Cost Reprogrammable FPGA Architecture. FPGA 1999: 3-12 - [e2]Sinan Kaptanoglu, Steve Trimberger:
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999. ACM 1999, ISBN 1-58113-088-0 [contents] - 1998
- [c2]Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor:
Constraints from Hell: How to Tell Makes a Good FPGA (Panel). FPGA 1998: 117-119 - [e1]Jason Cong, Sinan Kaptanoglu:
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998. ACM 1998, ISBN 0-89791-978-5 [contents] - 1990
- [j1]John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya:
Two-dimensional IC layout compaction based on topological design rule checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 260-275 (1990) - [c1]Jonathan W. Greene, Vwani P. Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal:
Segmented Channel Routing. DAC 1990: 567-572
Coauthor Index
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