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ORCIDLana Josipovic
Person information
- affiliation: ETH Zurich, Switzerland
- affiliation (former): EPFL, Lausanne, Switzerland
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2020 – today
- 2024
[b2]Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipovic, Zhufei Chu:
FPGA EDA - Design Principles and Implementation. Springer 2024, ISBN 978-981-99-7754-3, pp. 3-227- [c26]Andrea Guerrieri
, Srijeet Guha, Lana Josipovic, Paolo Ienne:
DynaRapid: From C to FPGA in a Few Seconds. FPGA 2024: 40 - [c25]Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. FPGA 2024: 44-54 - [c24]Jiahui Xu, Lana Josipovic:
Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. FPGA 2024: 188-198 - [c23]Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne:
DynaRapid: Fast-Tracking from C to Routed Circuits. FPL 2024: 24-32 - [c22]Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, Lana Josipovic:
Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits. FPL 2024: 118-125 - [e1]Lana Josipovic, Peipei Zhou, Shreejith Shanker, João M. P. Cardoso, Jason Anderson, Shibata Yuichiro:
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2024, Porto, Portugal, June 19-21, 2024. ACM 2024 [contents] - 2023
- [j6]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 16(4): 54:1-54:27 (2023) - [j5]Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides:
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16(4): 55:1-55:32 (2023) - [c21]Carmine Rizzi, Andrea Guerrieri, Lana Josipovic:
An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits. DAC 2023: 1-6 - [c20]Jiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic:
Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. FPGA 2023: 27-37 - [c19]Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. FPGA 2023: 39-45 - [c18]Hanyu Wang, Carmine Rizzi, Lana Josipovic:
MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. ICCAD 2023: 1-9 - [c17]Jiahui Xu, Lana Josipovic:
Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. ICCAD 2023: 1-9 - 2022
- [j4]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 628-641 (2022) - [j3]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
From C/C++ Code to High-Performance Dataflow Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2142-2155 (2022) - [j2]Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 15(1): 4:1-4:32 (2022) - [c16]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. FCCM 2022: 1-9 - [c15]Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson:
Dynamic Inter-Block Scheduling for HLS. FPL 2022: 243-252 - [c14]Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne:
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. FPL 2022: 253-261 - [c13]Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic:
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. FPL 2022: 375-383 - [c12]Jiantao Liu, Carmine Rizzi, Lana Josipovic:
Load-Store Queue Sizing for Efficient Dataflow Circuits. FPT 2022: 1-9 - [c11]Jürgen Becker, Lana Josipovic, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan:
29th Reconfigurable Architectures Workshop (RAW 2022). IPDPS Workshops 2022: 65-66 - 2021
- [b1]Lana Josipovic:
High-Level Synthesis of Dynamically Scheduled Circuits. EPFL, Switzerland, 2021 - [c10]Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne:
Resource Sharing in Dataflow Circuits. FPGA 2021: 226 - 2020
- [c9]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA 2020: 1-10 - [c8]Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA 2020: 186-196 - [c7]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298
2010 – 2019
- 2019
- [c6]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Speculative Dataflow Circuits. FPGA 2019: 162-171 - [c5]Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne:
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT 2019: 197-205 - 2018
- [c4]Lana Josipovic, Radhika Ghosal, Paolo Ienne:
Dynamically Scheduled High-level Synthesis. FPGA 2018: 127-136 - 2017
- [j1]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16(5s): 125:1-125:19 (2017) - [c3]Lana Josipovic, Philip Brisk, Paolo Ienne:
From C to elastic circuits. ACSSC 2017: 121-125 - [c2]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM 2017: 134 - 2016
- [c1]Lana Josipovic, Nithin George, Paolo Ienne:
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT 2016: 177-180
Coauthor Index
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last updated on 2024-10-22 21:13 CEST by the dblp team
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