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ORCIDYukihiro Iguchi
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2020 – today
- 2021
[j8]Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi:
Classification Functions for Handwritten Digit Recognition. IEICE Trans. Inf. Syst. 104-D(8): 1076-1082 (2021)- [c22]Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi:
A Design Method for Multiclass Classifiers. ISMVL 2021: 148-153 - 2020
- [c21]Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi:
Handwritten Digit Recognition Based on Classification Functions. ISMVL 2020: 124-129
2010 – 2019
- 2017
- [c20]Tsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi:
An algorithm to find optimum support-reducing decompositions for index generation functions. DATE 2017: 812-817 - 2014
- [j7]Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi:
A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2427-2433 (2014) - [c19]Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi:
A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions. ISMVL 2014: 7-12 - 2011
- [c18]Koki Shirakawa, Takashi Uemura, Yukihiro Iguchi:
A Realization Method of Forward Converters from Multiple-Precision Binary Numbers to Residue Numbers with Arbitrary Mutable Modulus. ISMVL 2011: 268-273
2000 – 2009
- 2008
- [c17]Tsutomu Sasao, Yukihiro Iguchi:
On the Complexity of Error Detection Functions for Redundant Residue Number Systems. DSD 2008: 880-887 - 2007
- [j6]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Design Methods of Radix Converters Using Arithmetic Decompositions. IEICE Trans. Inf. Syst. 90-D(6): 905-914 (2007) - [j5]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. J. Multiple Valued Log. Soft Comput. 13(4-6): 503-520 (2007) - [c16]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. ISMVL 2007: 32 - 2006
- [j4]Hui Qin, Tsutomu Sasao, Yukihiro Iguchi:
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA. IEICE Trans. Inf. Syst. 89-D(3): 1139-1147 (2006) - [c15]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Designs of Radix Converters Using Arithmetic Decompositions. ISMVL 2006: 3 - 2005
- [c14]Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki:
On LUT Cascade Realizations of FIR Filters. DSD 2005: 467-475 - [c13]Hui Qin, Tsutomu Sasao, Yukihiro Iguchi:
An FPGA design of AES encryption circuit with 128-bit keys. ACM Great Lakes Symposium on VLSI 2005: 147-151 - [c12]Yukihiro Iguchi, Tsutomu Sasao:
Hardware to Compute Walsh Coefficients. ISMVL 2005: 75-81 - 2004
- [j3]Atsumu Iseno, Yukihiro Iguchi, Tsutomu Sasao:
Fault Diagnosis for RAMs Using Walsh Spectrum. IEICE Trans. Inf. Syst. 87-D(3): 592-600 (2004) - [c11]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. ISMVL 2004: 302-308 - 2003
- [c10]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Evaluation of multiple-output logic functions using decision diagrams. ASP-DAC 2003: 312-315 - 2002
- [j2]Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi:
Bi-Partition of Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2693-2700 (2002) - [c9]Atsumu Iseno, Yukihiro Iguchi:
A Method for Storing Fail Bit Maps in Burn-in Memory Testers. DELTA 2002: 142-148 - [c8]Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Representations of Logic Functions Using QRMDDs. ISMVL 2002: 261-269 - [c7]Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS 2002: 379-384 - 2001
- [c6]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Realization of Multiple-Output Functions by Reconfigurable Cascades. ICCD 2001: 388-393 - 2000
- [c5]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno:
A hardware simulation engine based on decision diagrams (short paper). ASP-DAC 2000: 73-76 - [c4]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Implementation of Multiple-Output Functions Using PQMDDs. ISMVL 2000: 199-205
1990 – 1999
- 1999
- [c3]Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno:
Realization of Regular Ternary Logic Functions. ASP-DAC 1999: 331- - 1997
- [c2]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On properties of Kleene TDDs. ASP-DAC 1997: 473-476 - [c1]Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Decomposition of Kleene TDDs. Asian Test Symposium 1997: 234-
1980 – 1989
- 1989
- [j1]Yukihiro Iguchi, Masao Mukaidono:
Maximum PLA folding using inverters. Syst. Comput. Jpn. 20(4): 1-10 (1989)
Coauthor Index
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