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Kizheppatt Vipin
Person information
- affiliation: Nazarbayev University, Astana, Kazakhstan
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2020 – today
- 2024
- [j6]Indu Chandran
, Kizheppatt Vipin:
Multi-UAV Networks for Disaster Monitoring: Challenges and Opportunities from a Network Perspective. SN Comput. Sci. 5(5): 519 (2024) - 2023
- [c28]Muhammad Irfan, Kizheppatt Vipin, Rizwan Qureshi:
Accelerating DNA Sequence Analysis using Content-Addressable Memory in FPGAs. SmartCloud 2023: 69-72 - 2022
- [c27]Aakanksha Tewari, Neelam Singh, Sumit Jagdish Darak, Vipin Kizheppatt, Mohammed Sajjad Jafri:
Reconfigurable Wireless PHY with Dynamically Controlled Out-of-Band Emission on Zynq SoC. MWSCAS 2022: 1-4 - 2021
- [c26]Muhammad Irfan
, Kizheppatt Vipin
, Ray C. C. Cheung
:
On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration. ARC 2021: 305-314 - 2020
- [c25]Arshyn Zhanbolatov
, Kizheppatt Vipin
, Aresh Dadlani
, Dmitriy Fedorov:
StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures. ARC 2020: 361-375 - [c24]Xiangwei Li
, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain
:
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j5]Kuladeep Sai Reddy
, Kizheppatt Vipin
:
OpenNoC: An Open-Source NoC Infrastructure for FPGA-Based Hardware Acceleration. IEEE Embed. Syst. Lett. 11(4): 123-126 (2019) - [j4]Kizheppatt Vipin
:
AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation. Int. J. Reconfigurable Comput. 2019: 7239858:1-7239858:9 (2019) - [c23]Kizheppatt Vipin:
ZyNet: Automating Deep Neural Network Implementation on Low-Cost Reconfigurable Edge Computing Platforms. FPT 2019: 323-326 - [c22]Marzhan Bekbolat, Sabina Kairatova, Ayan Shymyrbay, Kizheppatt Vipin:
HBLast: An Open-Source FPGA Library for DNA Sequencing Acceleration. IPDPS Workshops 2019: 79-82 - [c21]Alex Pappachen James, Bhaskar Choubey, Kizheppatt Vipin:
Reconfigurable Threshold Logic Networks in FPGA for Moving Object Detection. MWSCAS 2019: 989-992 - 2018
- [j3]Kizheppatt Vipin, Suhaib A. Fahmy
:
FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications. ACM Comput. Surv. 51(4): 72:1-72:39 (2018) - [c20]Kizheppatt Vipin:
CANNoC: An open-source NoC architecture for ECU consolidation. MWSCAS 2018: 940-943 - [i1]Irina Dolzhikova, Khaled N. Salama, Vipin Kizheppatt, Alex Pappachen James:
Memristor-based Synaptic Sampling Machines. CoRR abs/1808.00679 (2018) - 2017
- [j2]Mikhail Asiatici
, Nithin George, Kizheppatt Vipin
, Suhaib A. Fahmy
, Paolo Ienne:
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017) - [c19]Kizheppatt Vipin, Jan Gray, Nachiket Kapre:
Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs. FPL 2017: 1-8 - 2016
- [c18]Mikhail Asiatici, Nithin George, Kizheppatt Vipin
, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2 - [c17]Malte Vesper, Dirk Koch, Kizheppatt Vipin
, Suhaib A. Fahmy:
JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. FPL 2016: 1-9 - 2015
- [b1]Vipin Kizheppatt:
Design automation for partially reconfigurable adaptive systems. Nanyang Technological University, Singapore, 2015 - [c16]Kizheppatt Vipin
, Suhaib A. Fahmy:
Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq. AHS 2015: 1-8 - [c15]Suhaib A. Fahmy, Kizheppatt Vipin
, Shanker Shreejith
:
Virtualized FPGA Accelerators for Efficient Cloud Computing. CloudCom 2015: 430-435 - [c14]Shanker Shreejith
, Bhaskar Banarjee, Kizheppatt Vipin
, Suhaib A. Fahmy:
Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA. CrownCom 2015: 427-437 - [c13]Amit Kulkarni, Kizheppatt Vipin
, Dirk Stroobandt:
MiCAP: a custom reconfiguration controller for dynamic circuit specialization. ReConFig 2015: 1-6 - 2014
- [j1]Kizheppatt Vipin
, Suhaib A. Fahmy
:
ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq. IEEE Embed. Syst. Lett. 6(3): 41-44 (2014) - [c12]Kizheppatt Vipin
, Shanker Shreejith
, Suhaib A. Fahmy
, Arvind Easwaran
:
Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs. CPSNA 2014: 31-36 - [c11]Kizheppatt Vipin
, Suhaib A. Fahmy
:
Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq. FCCM 2014: 202-205 - [c10]Kizheppatt Vipin
, Suhaib A. Fahmy
:
DyRACT: A partial reconfiguration enabled accelerator and test platform. FPL 2014: 1-7 - 2013
- [c9]Shanker Shreejith
, Kizheppatt Vipin, Suhaib A. Fahmy, Martin Lukasiewycz:
An approach for redundancy in FlexRay networks using FPGA partial reconfiguration. DATE 2013: 721-724 - [c8]Kizheppatt Vipin
, Suhaib A. Fahmy
:
An Approach to a Fully Automated Partial Reconfiguration Design Flow. FCCM 2013: 231 - [c7]Kizheppatt Vipin
, Shanker Shreejith
, Dulitha Gunasekera, Suhaib A. Fahmy
, Nachiket Kapre:
System-level FPGA device driver with high-level synthesis support. FPT 2013: 128-135 - [c6]Kizheppatt Vipin
, Suhaib A. Fahmy
:
Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems. IPDPS Workshops 2013: 172-181 - 2012
- [c5]Kizheppatt Vipin
, Suhaib A. Fahmy
:
Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration. ARC 2012: 13-25 - [c4]Kizheppatt Vipin
, Suhaib A. Fahmy
:
A high speed open source controller for FPGA Partial Reconfiguration. FPT 2012: 61-66 - 2011
- [c3]Kizheppatt Vipin
, Suhaib A. Fahmy
:
Enabling high level design of adaptive systems with partial reconfiguration. FPT 2011: 1-4 - [c2]Kizheppatt Vipin
, Suhaib A. Fahmy
:
A threat-based Connect6 implementation on FPGA. FPT 2011: 1-4 - [c1]Kizheppatt Vipin
, Suhaib A. Fahmy
:
Efficient region allocation for adaptive partial reconfiguration. FPT 2011: 1-6
Coauthor Index
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last updated on 2024-07-05 21:05 CEST by the dblp team
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