survey

FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications

Authors:

Kizheppatt Vipin,

Suhaib A. FahmyAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 51, Issue 4

Article No.: 72, Pages 1 - 39

https://doi.org/10.1145/3193827

Published: 25 July 2018 Publication History

Abstract

Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.

References

[1]

S. N. Adya and I. L. Markov. 2001. Fixed-outline floorplanning through better local search. In Proceedings of ACM/IEEE International Conference on Computer Design. 328--334.

Digital Library

[2]

A. Agne, M. Happe, A. Keller, E. LÃbbers, B. Plattner, M. Platzner, and C. Plessl. 2014. ReconOS: An operating system approach for reconfigurable computing. IEEE Micro 34, 1 (Jan. 2014), 60--71.

[3]

Altera. 2013a. Design Planning for Partial Reconfiguration. Altera.

[4]

Altera. 2013b. Quartus II Handbook Version 13.1. Altera.

[5]

Altera. 2016a. Arria 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide. Altera.

[6]

Altera. 2016b. Quartus Prime Standard Edition Handbook. Altera.

[7]

Altera. 2017. ug-partrecon: Partial Reconfiguration IP Core. Altera.

[8]

Atmel. 2013. AT40K05, AT40K10, AT40K20, AT40K40 Datasheet. Altera.

[9]

Ramzi Ayadi, Bouraoui Ouni, and Abdellatif Mtibaa. 2014. Integrated temporal partitioning and partial reconfiguration techniques for design latency improvement. Evolving Systems 5, 2 (Jun. 2014), 133--141.

[10]

R. Backasch, G. Hempel, S. Werner, S. Groppe, and T. Pionteck. 2014. Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation. In Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig14). 1--6.

[11]

P. Banerjee, M. Sangtani, and S. Sur-Kolay. 2011. Floorplanning for partially reconfigurable FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 30, 1 (Jan. 2011), 8--17.

Digital Library

[12]

K. Bazargan, R. Kastner, and M. Sarrafzadeh. 2000. Fast template placement for reconfigurable computing systems. IEEE Design and Test of Computers 17, 1 (Jan. 2000), 68--83.

Digital Library

[13]

T. Becker, W. Luk, and P. Y. K. Cheung. 2007. Enhancing relocatability of partial bitstreams for run-time reconfiguration. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM).

Digital Library

[14]

C. Beckhoff, D. Koch, and J. Torresen. 2012. GoAhead: A partial reconfiguration framework. In Proceeding of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). 37--44.

Digital Library

[15]

C. Beckhoff, D. Koch, and J. Torresen. 2014. Portable module relocation and bitstream compression for Xilinx FPGAs. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL).

[16]

C. Beckhoff, D. Koch, and J. Torreson. 2013. Automatic floorplanning and interface synthesis of island style reconfigurable systems with GOAHEAD. In Proceedings of International Conference on Architecture of Computing Systems (ARCS). Springer Berlin, 303--316.

Digital Library

[17]

S. U. Bhandari, S. Subbaraman, S. Pujari, and R. Mahajan. 2009. Real time video processing on FPGA using on the fly partial reconfiguration. In Proceedings of International Conference on Signal Processing Systems (ICSPS). 244--247.

Digital Library

[18]

M. Birla and K. N. Vikram. 2008. Partial run-time reconfiguration of FPGA for computer vision applications. In Proceedings of IEEE International Symposium on Parallel and Distributed Processing (IPDPS).

[19]

M. Boden, T. Fiebig, M. Reiband, and P. Reichel. 2008. GePaRD—A high-level generation flow for partially reconfigurable designs. In Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Digital Library

[20]

C. Bolchini, A. Miele, and M. D. Santambrogio. 2007a. TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs. In Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT).

Digital Library

[21]

C. Bolchini, D. Quarta, and M. D. Santambrogio. 2007b. SEU mitigation for SRAM-based FPGAs through dynamic partial reconfiguration. In Proceedings of ACM Great Lakes Symposium on VLSI.

Digital Library

[22]

S. Bouchoux, E. Bourennane, and M. Paindavoine. 2004. Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA. In Proceedings of International Conference on Image Processing (ICIP).

[23]

G. Brebner. 1996. A Virtual Hardware Operating System for the Xilinx XC6200. Springer Berlin, 327--336.

Digital Library

[24]

S. Byma, J. G. Steffan, H. Bannazadeh, A. Leon-Garcia, and P. Chow. 2014. FPGAs in the cloud: Booting virtualized hardware accelerators with OpenStack. In Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). 110--116.

Digital Library

[25]

D. Capalija and T. S. Abdelrahman. 2013. A high-performance overlay architecture for pipelined execution of data flow graphs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL).

[26]

C. Carmichael. 2000. XAPP216: Correcting Single-Event Upsets Through Virtex Partial Configuration. Xilinx Inc.

[27]

C. Carmichael. 2006. XAPP197: Triple Module Redundancy Design Techniques for Virtex FPGAs. Xilinx Inc.

[28]

M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori. 2003. Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs. IEEE Transactions on Nuclear Science 50, 6 (Dec. 2003), 2088--2094.

[29]

George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, and Dionisios Pnevmatikatos. 2015. Hardware Task Scheduling for Partially Reconfigurable FPGAs. Springer International Publishing, Cham, 487--498.

[30]

C. S. Choi and H. Lee. 2006. An reconfigurable FIR filter design on a partial reconfiguration platform. In Proceedings of Communications and Electronics (ICCE).

[31]

W. Chong, S. Ogata, M. Hariyama, and M. Kameyama. 2005. Architecture of a multi-context FPGA using reconfigurable context memory. In Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Digital Library

[32]

C. B. Ciobanu, D. N. Pnevmatikatos, K. D. Papadimitriou, and G. N. Gaydadjiev. 2013. FASTER run-time reconfiguration management. In Proceedings of ACM International Conference on Supercomputing (ICS’13). ACM, 463--464.

Digital Library

[33]

C. Claus, F. H. Muller, J. Zeppenfeld, and W. Stechele. 2007a. A new framework to accelerate Virtex-II Pro dynamic partial self reconfiguration. In Proceedings of IEEE International Symposium on Parallel 8 Distributed Processing, Workshops and PhD Forum (IPDPSW).

[34]

C. Claus, W. Stechele, and A. Herkersdorf. 2007b. Autovision—A run-time reconfigurable MPSoC architecture for future driver assistance systems. Information Technology 49 (2007), 181--186.

[35]

C. Claus, J. Zeppenfeld, F. Muller, and W. Stechele. 2007c. Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. In Proceedings of Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE).

Digital Library

[36]

C. Claus, B. Zhang, W. Stechele, L. Braun, M. Hubner, and J. Becker. 2008. A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL). 535--538.

[37]

K. Compton and S. Hauck. 2002. Reconfigurable computing: A survey of systems and software. ACM Computing Surveys (CSUR) 34, 2 (June 2002), 171--210.

Digital Library

[38]

J. Coole and G. Stitt. 2015. Adjustable-cost overlays for runtime compilation. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM). 21--24.

Digital Library

[39]

A. DeHon. 1996. DPGA utilization and application. In Proceedings of ACM/SIGDA International Symposium on FPGAs.

Digital Library

[40]

A. DeHon and M. J Wilson. 2004. Nanowire-based sublithographic programmable logic arrays. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). 123--132.

Digital Library

[41]

J. P. Delahaye, J. Palicot, C. Moy, and P. Leray. 2007. Partial reconfiguration of FPGAs for dynamical reconfiguration of a software radio platform. In Proceedings of IST Mobile and Wireless Comms. Summit.

[42]

J. Delorme, J. Martin, A. Nafkha, C. Moy, F. Clermidy, P. Leray, and J. Palicot. 2008. A FPGA partial reconfiguration design approach for cognitive radio based on NoC architecture. In Proceedings of International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference. 355--358.

[43]

Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, MarcoDomenico Santambrogio, and Donatella Sciuto. 2007. Caronte: A methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platforms. In VLSI-Soc: From Systems To Silicon. Vol. 240. Springer US, 87--109.

[44]

E. El-Araby, I. Gonzale, and T. El-Ghazawi. 2007. Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing. In Proceedings of International Workshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA).

Digital Library

[45]

E. Eto. 2007. XAPP290: Difference-Based Partial Reconfiguration. Technical Report. Xilinx Inc.

[46]

S. A. Fahmy, J. Lotze, J. Noguera, L. Doyle, and R. Esser. 2009. Generic software framework for adaptive applications on FPGAs. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 55--62.

Digital Library

[47]

S. A. Fahmy, K. Vipin, and S. Shreejith. 2015. Virtualized FPGA accelerators for efficient cloud computing. In Proceedings of IEEE International Conference on Cloud Computing Technology and Science, Vancouver, Canada. 430--35.

Digital Library

[48]

Y. Feng and D. P. Mehta. 2006. Heterogeneous floorplanning for FPGAs. In Proceedings of International Conference on VLSI Design.

Digital Library

[49]

A. A. Fohlich and L. F. Wanner. 2008. Operating system support for wireless sensor networks. Journal of Computer Science 4, 4 (2008), 272--281.

[50]

D. De La Fuente, J. Barba, X. Pena, J. C. Lopez, P. Penil, and P. P. Sanchez. 2015. Building a dynamically reconfigurable system through a high development flow. In Proceedings of Forum on Specification and Design Languages (FDL).

[51]

S. Ganesan and R. Vemuri. 2000. An integrated temporal partitioning and partial reconfiguration technique for design latency improvement. In Proceedings of Design, Automation and Test in Europe (DATE). 320--325.

Digital Library

[52]

W. Gao, K. Kugel, R. Manner, N. Abel, N. Meier, and U. Kebschull. 2009. DPR in high energy physics. In Proceedings of Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE).

Digital Library

[53]

D. Gohringer, J. Noguera, and J. Becker. 2010. Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. In Proceedings of IEEE International Symposium on Parallel 8 Distributed Processing, Workshops and PhD Forum (IPDPSW).

[54]

M. Gokhale and D. Gomersall. 1997. High level compilation for fine grained FPGAs. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 165--173.

Digital Library

[55]

L. Gong and O. Diessel. 2011. ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration. In Proceeding of International Conference on Field-Programmable Technology. 1--8.

[56]

S. Guccione, D. Levi, and P. Sundararajan. 2004. JBits: Java Based Interface for Reconfigurable Computing. Technical Report. Xilinx Inc.

[57]

G. Haiyun and C. Shurong. 2008. Partial reconfiguration bitstream compression for Virtex FPGAs. In Proceedings of Congress on Image and Signal Processing (CISP).

Digital Library

[58]

S. Gimle Hansen, D. Koch, and J. Torresen. 2011. High speed partial run-time reconfiguration using enhanced ICAP hard macro. In Proceedings of IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum.

Digital Library

[59]

J. Harkin, T. M. Mcginnity, and L. P. Maguire. 2004. Modeling and optimizing run-time reconfiguration using evolutionary computation. ACM Transactions on Embedded Computing Systems (TECS) 3, 4 (Nov. 2004), 661--685.

Digital Library

[60]

S. Hauck, Z. Li, and E. Schwabe. 1998. Configuration compression for the Xilinx XC6200 FPGA. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM).

Digital Library

[61]

S. Hauck, Z. Li, and E. Schwabe. 1999. Configuration compression for the Xilinx XC6200 FPGA. In Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Digital Library

[62]

J. R. Hauser and J. Wawrzynek. 1997. Garp: A MIPS processor with a reconfigurable coprocessor. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM).

Digital Library

[63]

J. Heiner, B. Sellers, M. Wirthlin, and J. Kalb. 2009. FPGA partial reconfiguration via configuration scrubbing. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL).

[64]

E. L. Horta and J. W. Lockwood. 2001. PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of FIeld Programmable Gate Arrays (FPGA). Washington University.

[65]

D. How and S. Atsatt. 2016. Sectors: Divide 8 conquer and softwarization in the design and validation of the Stratix-10 FPGA. In Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[66]

M. Huebner, T. Becker, and J. Becker. 2004. Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. In Proceedings of Symposium on Integrated Circuits and Systems Design. 28--32.

Digital Library

[67]

C. Huriaux, O. Sentieys, and R. Tessier. 2014. FPGA architecture support for heterogeneous, relocatable partial bitstreams. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL).

[68]

H. M. Hussain, K. Benkrid, A. Ebrahim, A. T. Erdogan, and H. Seker. 2012. Novel dynamic partial reconfiguration implementation of K-means clustering on FPGAs: Comparative results with GPPs and GPUs. International Journal of Reconfigurable Computing (IJRC) 2012, Article ID 135926 (Jan.2012), 15 pages.

Digital Library

[69]

H. Hussain, K. Benkrid, and H. Seker. 2014. Novel dynamic partial reconfiguration implementations of the support vector machine classifier on FPGA. Turkish Journal of Electrical Engineering 8 Computer Sciences 24 (2014), 3371--3387.

[70]

Intel. 2017a. UG-20066: Partial Reconfiguration Solutions IP User Guide.

[71]

Intel. 2017b. UG-OCL002 Intel FPGA SDK for OpenCL: Programing Guide.

[72]

A. K. Jain, X. Li, P. Singhai, D. L. Maskell, and S. A. Fahmy. 2016a. DeCO: A DSP block based FPGA accelerator overlay with low overhead interconnect. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM). 1--8.

[73]

A. K. Jain, D. L. Maskell, and S. A. Fahmy. 2016b. Throughput oriented FPGA overlays using DSP blocks. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). 1628--1633.

Digital Library

[74]

A. Jara-Berrocal and A. Gordon-Ross. 2009. Runtime temporal partitioning assembly to reduce FPGA reconfiguration time. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Digital Library

[75]

C. Kachris and D. Soudris. 2016. A survey on reconfigurable accelerators for cloud computing. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL). 1--10.

[76]

H. Kalte, G. Lee, M. Porrmann, and U. Rückert. 2005. REPLICA: A bitstream manipulation filter for module relocation in partial reconfigurable systems. In Proceedings of IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Digital Library

[77]

H. Kalte and M. Porrmann. 2006. REPLICA2Pro: Task relocation by bitstream manipulation in Virtex-II/Pro FPGAs. In Proceedings of Conference on Computing Frontiers.

Digital Library

[78]

I. Kennedy. 2003. Exploiting redundancy to speedup reconfiguration of an FPGA. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 262--271.

[79]

R. Khraisha and J. Lee. 2010. A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration. In Proceedings of IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP).

[80]

D. Koch, J. Torresen, C. Beckhoff, D. Ziener, C. Dennl, V. Breuer, J. Teich, M. Feilen, and W. Stechele. 2012. Partial reconfiguration on FPGAs in practice; Tools and applications. In Proceedings of ARCS Workshops (ARCS). 1--12.

[81]

M. Koester, W. Luk, J. Hagemeyer, and M. Porrmann. 2009. Design optimizations to improve placeability of partial reconfiguration modules. In Proceedings of Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE).

Digital Library

[82]

B. Krill, A. Amira, A. Ahmad, and H. Rabah. 2010. A new FPGA-based dynamic partial reconfiguration design flow and environment for image processing applications. In Proceedings of European Workshop on Visual Information Processing (EUVIP). 226--231.

[83]

R. Kumar and A. Gordon-Ross. 2013. PRML: A modeling language for rapid design exploration of partially reconfigurable FPGAs. In Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). 117--120.

Digital Library

[84]

R. Kumar and A. Gordon-Ross. 2015. An automated high-level design framework for partially reconfigurable FPGAs. In Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW).

Digital Library

[85]

Lattice Corp. 2003. ORCA Series 4 FPGAs. Lattice Semiconductor Corporation.

[86]

Z. Li, K. Compton, and S. Hauck. 2000. Configuration caching management techniques for reconfigurable computing. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM).

Digital Library

[87]

Z. Li and S. Hauck. 2001. Configuration compression for Virtex FPGAs. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM).

Digital Library

[88]

J. Lipsky. 2015. Retrieved from http://www.eetimes.com/document.asp?doc_id=1325499.

[89]

M. Liu, W. Kuehn, Z. Lu, and A. Jantsch. 2009a. Run-time partial reconfiguration speed investigation and architectural design space exploration. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL).

[90]

S. Liu, R. N. Pittman, and A. Forin. 2009b. Minimizing Partial Reconfiguration Overhead with Fully Streaming DMA Engines and Intelligent ICAP Controller. Technical Report MSR-TR-2009- 150. Microsoft Research.

[91]

J. W. Lockwood, N. Naufel, J. S. Turner, and D. E. Taylor. 2001. Reprogrammable network packet processing on the field programmable port extender (FPX). In Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA).

Digital Library

[92]

J. Lotze, S. A. Fahmy, J. Noguera, B. Ozgul, L. Doyle, and R. Esser. 2009. Development framework for implementing FPGA-based cognitive network nodes. In Proceedings of IEEE Global Telecommunications Conference (GLOBECOM).

Digital Library

[93]

Y. Lu, T. Marconi, K. Bertels, and G. Gaydadjiev. 2009. Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems. Springer Berlin, 216--230.

Digital Library

[94]

Y. Lu, T. Marconi, G. N. Gaydadjiev, K. Bertels, and R. J. Meeuws. 2008. A self-adaptive on-line task placement algorithm for partially reconfigurable systems. In Proceedings of Parallel and Distributed Processing Symposium (IPDPS).

Digital Library

[95]

W. Luk, N. Shirazi, and P. Y. K. Cheung. 1996. Modelling and optimising run-time reconfigurable systems. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM).

[96]

W. Luk, N. Shirazi, and P. Y. K. Cheung. 1997. Compilation tools for run-time reconfigurable designs. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 56--65.

Digital Library

[97]

P. Lysaght, B. Blodget, J. Mason, J. Young, and B. Bridgford. 2006. Invited paper: Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL).

[98]

P. Lysaght and J. Stockwood. 1996. A simulation tool for dynamically reconfigurable field programmable gate arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 4, 3 (Sept. 1996), 381--390.

Digital Library

[99]

M. Majer, J. Teich, A. Ahmadinia, and C. Bobda. 2007. The Erlangen slot machine: A dynamically reconfigurable FPGA-based computer. The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 47, 1 (Apr. 2007), 15--31.

Digital Library

[100]

P. Manet, D. Maufroid, L. Tosi, G. Gailliard, O. Mulertt, M. D. Ciano, J. D. Legat, D. Aulagnier, C. Gamrat, R. Liberati, V. L. Barba, P. Cuvelier, B. Rousseau, and P. Gelineau. 2008. An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications. EURASIP Journal on Embedded Systems 2008, Article ID 367860 (2008), 11 pages.

Digital Library

[101]

A. Montone, M. D. Santambrogio, D. Sciuto, and S. O. Memik. 2010. Placement and floorplanning in dynamically reconfigurable FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 3, 4 (Nov. 2010), 24:11--24:34.

Digital Library

[102]

National. 1993. Configurable Logic Array (CLAy) Data Sheet. National Semiconductor.

[103]

B. Navas, I. Sander, and J. Oberg. 2013. The RecoBlock SoC platform: A flexible array of reusable run-time-reconfigurable IP-blocks. In Proceedings of Design, Automation 8 Test in Europe Conference 8 Exhibition. 833--838.

Digital Library

[104]

J. Noguera and I. O. Kennedy. 2007. Power reduction in network equipment through adaptive partial reconfiguration. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL). 240--245.

[105]

R. T. Ong. 1995. Programmable Logic Device which stores more than one configuration and means for switching configurations. US patent 5,426,378.

[106]

B. Osterloh, H. Michalik, S. A. Habinc, and B. Fiethe. 2009. Dynamic partial reconfiguration in space applications. In Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems.

Digital Library

[107]

J. H. Pan, T. Mitra, and W. Wong. 2004. Configuration bitstream compression for dynamically reconfigurable FPGAs. In Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD).

Digital Library

[108]

K. Papadimitriou, A. Anyfantis, and A. Dollas. 2010. An effective framework to evaluate dynamic partial reconfiguration in FPGA systems. IEEE Transactions on Instrumentation and Measurement 59, 6 (June 2010), 1642--1651.

[109]

K. Papadimitriou, A. Dollas, and S. Hauck. 2011. Performance of partial reconfiguration in FPGA systems: A survey and cost model. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4, 4 (Dec. 2011), 36:1--36:24.

Digital Library

[110]

C. Patterson. 2000. High performance DES encryption in Virtex FPGAs using JBits. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 113--121.

Digital Library

[111]

M. Peattie. 2009. Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode. Technical Report. Xilinx Inc.

[112]

T. H. Pham, S. A. Fahmy, and I. V. McLoughlin. 2017. An end-to-end multi-standard OFDM transceiver architecture using FPGA partial reconfiguration. IEEE Access 5 (2017), 21002--21015.

[113]

M. Platzner, J. Teich, and N. Wehn. 2010. Dynamically Reconfigurable Systems. Springer Netherlands.

Digital Library

[114]

A. Purgato, D. Tantillo, M. Rabozzi, D. Sciuto, and M. D. Santambrogio. 2016. Resource-efficient scheduling for partially-reconfigurable FPGA-based systems. In Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). 189--197.

[115]

A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J. Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Y. Xiao, and D. Burger. 2014. A reconfigurable fabric for accelerating large-scale datacenter services. In Proceedings of the International Symposium on Computer Architecture. 13--24.

Digital Library

[116]

S. Raaijmakers and S. Wong. 2007. Run-time partial reconfiguration for removal, placement and routing on the Virtex-II Pro. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL).

[117]

M. Rabozzi, R. Cattaneo, T. Becker, W. Luk, and M. D. Santambrogio. 2015. Relocation-aware floorplanning for partially-reconfigurable FPGA-based systems. In Proceedings of IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW). 97--104.

Digital Library

[118]

M. Rabozzi, J. Lillis, and M. D. Santambrogio. 2014. Floorplanning for partially-reconfigurable FPGA systems via mixed-integer linear programming. In Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Digital Library

[119]

V. Rana, S. Murali, D. Atienza, M. D. Santambrogio, L. Benini, and D. Sciuto. 2009. Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. In Proceedings of IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Digital Library

[120]

T. A. Reis and A. A. Fröhlich. 2009. Operating system support for difference-based partial hardware reconfiguration. In Proceedings of IEEE/IFIP International Symposium on Rapid System Prototyping (RSP). 75--80.

Digital Library

[121]

M. D. Santambrogio, V. Rana, and D. Sciuto. 2008. Operating system support for online partial dynamic reconfiguration management. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL). 455--458.

[122]

A. Schallenberg, W. Nebel, A. Herrholz, P.A. Hartmann, K. Grüttner, and F. Oppenheimer. 2010. Dynamically Reconfigurable Systems (1st ed.). Springer, Chapter POLYDYN-Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs, 139--158.

[123]

A. Schallenberg, W. Nebel, A. Herrholz, P. A. Hartmann, and F. Oppenheimer. 2009. OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). 970--975.

Digital Library

[124]

S. Shreejith, B. Banarjee, K. Vipin, and S. A. Fahmy. 2015. Dynamic cognitive radio on the Xilinx Zynq hybrid FPGA. In Proceedings of International Conference on Cognitive Radio Oriented Wireless Networks (CROWNCOM).

[125]

S. Shreejith and S. A. Fahmy. 2015. Security aware network controller for next generation automotive embedded systems. In Proceedings of Design Automation Conference (DAC).

Digital Library

[126]

S. Shreejith, K. Vipin, S. A. Fahmy, and M. Lukasiewycz. 2013. An approach for redundancy in FlexRay networks using FPGA partial reconfiguration. In Proceedings of the Design, Automation and Test in Europe Conference (DATE).

Digital Library

[127]

L. Singhal and E. Bozorgzadeh. 2007. Multi-layer floorplanning for reconfigurable designs. IET Computers 8 Digital Techniques 1, 4 (July 2007), 276--294.

[128]

G. S. Snider and R. S. Williams. 2007. Nano/CMOS architectures using a field-programmable nanowire interconnect. Nanotechnology 18, 3 (2007), 035204.

[129]

A. A. Sohanghpurwala, P. Athanas, T. Frangieh, and A. Wood. 2011. OpenPR: An open-source partial-reconfiguration toolkit for Xilinx FPGAs. In Proceedings of IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW). 228--235.

Digital Library

[130]

C. Steiger, H. Walder, and M. Platzner. 2004. Operating systems for reconfigurable embedded platforms: Online scheduling of real-time tasks. IEEE Trans. Comput. 53, 11 (Nov. 2004).

[131]

N. J. Steiner. 2008. Autonomous Computing Systems. Ph.D. Dissertation. Virginia Polytechnic Institute and State University.

[132]

N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas, and M. French. 2011. Torc: Towards an open-source tool flow. In Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA).

Digital Library

[133]

G. Stitt and J. Coole. 2011. Intermediate fabrics: Virtual architectures for near-instant FPGA compilation. IEEE Embedded Systems Letters 3, 3 (2011), 81--84.

Digital Library

[134]

Tabula. 2010. ABAX Product Brief. Technical Report. Tabula.

[135]

H. Taghipour, J. Frounchi, and M. H. Zarifi. 2008. Design and implementation of MP3 decoder using partial dynamic reconfiguration on Virtex-4 FPGAs. In Proceedings of International Conference on Computer and Communication Engineering.

[136]

E. Tau, I. Eslick, D. Chen, J. Brown, and A. DeHon. 1995. A first generation DPGA implementation. In Proceedings of the Canadian Workshop on Field-Programmable Devices (FPD). 138--143.

[137]

T. J. Todman, G. A. Constantinides, S. J. E. Wilton, O. Mencer, W. Luk, and P. Y. K. Cheung. 2005. Reconfigurable computing: Architectures and design methods. IEE Proceedings—Computers and Digital Techniques 152, 2 (Mar. 2005), 193--207.

[138]

J. Torresen, G. A. Senland, and K. Glette. 2008. Partial reconfiguration applied in an on-line evolvable pattern recognition system. In Proceedings of The Nordic Microelectronics Event (NORCHIP).

[139]

S. Trimberger, D. Carberry, A. Johnson, and J. Wong. 1997. A time-multiplexed FPGA. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM). 22--28.

Digital Library

[140]

K. Vipin and S. A. Fahmy. 2011. Efficient region allocation for adaptive partial reconfiguration. In Proceedings of the International Conference on Field Programmable Technology (FPT). 1--6.

[141]

K. Vipin and S. A. Fahmy. 2012a. Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration. In Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC). 13--25.

Digital Library

[142]

K. Vipin and S. A. Fahmy. 2012b. A high speed open source controller for FPGA partial reconfiguration. In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT).

[143]

K. Vipin and S. A. Fahmy. 2013. An automated partitioning scheme for partial reconfiguration based adaptive systems. In Proceedings of Reconfigurable Architecture Workshop (RAW).

Digital Library

[144]

K. Vipin and S. A. Fahmy. 2014a. DyRACT: A partial reconfiguration enabled accelerator and test platform. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL).

[145]

K. Vipin and S. A. Fahmy. 2014b. ZyCAP: Efficient partial reconfiguration management on the Xilinx Zynq. IEEE Embedded Systems Letters 6, 3 (Sept. 2014), 41--44.

[146]

K. Vipin and S. A. Fahmy. 2015. Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[147]

F. Wang and J. J. Jean. 2012. Architecture and operating system support for two-dimensional runtime partial reconfiguration. The Journal of Supercomputing 59, 2 (2012), 610--635.

Digital Library

[148]

L. Wirbel. 2014. Xilinx SDAccel: A Unified Development Environment for Tomorrow’s Data Center. Technical Report. Xilinx Inc.

[149]

M. J. Wirthlin and B. L. Hutchings. 1995. A dynamic instruction set computer. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines.

Digital Library

[150]

Z. Xiao, D. Koch, and M. Lujan. 2016. A partial reconfiguration controller for Altera Stratix V FPGAs. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL).

[151]

Xilinx Inc. 1996. Programmable Logic Data Book.

[152]

Xilinx Inc. 2003. DS031: Virtex-II Platform FPGAs.

[153]

Xilinx Inc. 2004a. XAPP151: Virtex Series Configuration Architecture User Guide.

[154]

Xilinx Inc. 2004b. Xilinx Device Drivers Documentation. Xilinx Inc.

[155]

Xilinx Inc. 2006. DS280: OPB HWICAP. Xilinx Inc.

[156]

Xilinx Inc. 2008. UG070: Virtex-4 FPGA User Guide. Xilinx Inc.

[157]

Xilinx Inc. 2010. DS586: XPS HWICAP. Xilinx Inc.

[158]

Xilinx Inc. 2011a. DS083: Virtex-II Pro and Virtex-II Pro-X Platform FPGAs. Xilinx Inc.

[159]

Xilinx Inc. 2011b. UG360: Virtex 6 FPGA Configuration User Guide. Xilinx Inc.

[160]

Xilinx Inc. 2013a. UG585: Zynq-7000 All Programmable SoC Technical Reference Manual. Xilinx Inc.

[161]

Xilinx Inc. 2013b. UG682: PlanAhead User Guide. Xilinx Inc.

[162]

Xilinx Inc. 2014. UG910: Vivado Design Suite User Guide. Xilinx Inc.

[163]

Xilinx Inc. 2015. UG570: UltraScale Architecture Configuration. Xilinx Inc.

[164]

Xilinx Inc. 2016. UltraScale Architecture and Product Overview. Xilinx Inc.

[165]

Xilinx Inc. 2017a. UG1023: SDAccel Environment User Guide. Xilinx. Inc.

[166]

Xilinx Inc. 2017b. UG893: Vivado Design Suite User Guide. Xilinx Inc.

[167]

Xilinx Inc. 2017c. UG909: Vivado Design Suite User Guide Partial Reconfiguration. Xilinx Inc.

[168]

D. Yin, D. Unnikrishnan, Y. Liao, L. Gao, and R. Tessier. 2011. Customizing virtual networks with partial FPGA reconfiguration. ACM SIGCOMM Computer Communication Review 41, 1 (Jan. 2011), 57--64.

Digital Library

[169]

J. Yuan, S. Dong, X. Hong, and Y. Wu. 2005. LFF algorithm for heterogeneous FPGA floorplanning. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC). 1123--1126.

Digital Library

[170]

W. Zhang, N. K. Jha, and L. Shang. 2009. A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture. ACM Journal on Emerging Technologies in Computing Systems 5, 4 (2009), 16:1--16:30.

Digital Library

Cited By

Zhang GShao LWu HGu XZhang X(2025)Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable SystemIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2024.346831772:1(268-272)Online publication date: Jan-2025
https://doi.org/10.1109/TCSII.2024.3468317
Chen KYang CSun YTseng CFayazi MHe XFeng SYue YMudge TDreslinski RKim HBlaauw D(2025)DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFETIEEE Journal of Solid-State Circuits10.1109/JSSC.2024.343875860:2(672-684)Online publication date: Mar-2025
https://doi.org/10.1109/JSSC.2024.3438758
Crary CPiard WStitt GHicks BBean CBurlacu BBanzhaf W(2025)Using FPGA devices to accelerate the evaluation phase of tree-based genetic programming: an extended analysisGenetic Programming and Evolvable Machines10.1007/s10710-024-09505-226:1Online publication date: 1-Jun-2025
https://dl.acm.org/doi/10.1007/s10710-024-09505-2
Show More Cited By

Index Terms

FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
  2. Embedded and cyber-physical systems
    1. Embedded systems
2. Hardware
  1. Electronic design automation
    1. Methodologies for EDA
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Reconfigurable logic applications

Recommendations

ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge
Partial reconfiguration (PR) is a key enabler to the design and development of adaptive systems on modern Field Programmable Gate Array (FPGA) Systems-on-Chip (SoCs), allowing hardware to be adapted dynamically at runtime. Vendor-supported PR ...
Performance of partial reconfiguration in FPGA systems: A survey and a cost model

Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that ...
High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing
DSD '12: Proceedings of the 2012 15th Euromicro Conference on Digital System Design

The use of Field Programmable Gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, ...

Comments

Information & Contributors

Information

Published In

cover image ACM Computing Surveys

ACM Computing Surveys Volume 51, Issue 4

July 2019

765 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/3236632

Editor:
Sartaj Sahni
Department of Computer and Information Science and Engineering / University of Florida / Gainesville, FL 32611

Issue’s Table of Contents

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 July 2018

Accepted: 01 February 2018

Revised: 01 February 2018

Received: 01 December 2016

Published in CSUR Volume 51, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Survey
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

153
Total Citations
View Citations
3,005
Total Downloads

Downloads (Last 12 months)402
Downloads (Last 6 weeks)38

Reflects downloads up to 27 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Zhang GShao LWu HGu XZhang X(2025)Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable SystemIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2024.346831772:1(268-272)Online publication date: Jan-2025
https://doi.org/10.1109/TCSII.2024.3468317
Chen KYang CSun YTseng CFayazi MHe XFeng SYue YMudge TDreslinski RKim HBlaauw D(2025)DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFETIEEE Journal of Solid-State Circuits10.1109/JSSC.2024.343875860:2(672-684)Online publication date: Mar-2025
https://doi.org/10.1109/JSSC.2024.3438758
Crary CPiard WStitt GHicks BBean CBurlacu BBanzhaf W(2025)Using FPGA devices to accelerate the evaluation phase of tree-based genetic programming: an extended analysisGenetic Programming and Evolvable Machines10.1007/s10710-024-09505-226:1Online publication date: 1-Jun-2025
https://dl.acm.org/doi/10.1007/s10710-024-09505-2
Khan LIsanaka SLiou F(2024)FPGA-Based Sensors for Distributed Digital Manufacturing Systems: A State-of-the-Art ReviewSensors10.3390/s2423770924:23(7709)Online publication date: 2-Dec-2024
https://doi.org/10.3390/s24237709
Khan Mda Silva B(2024)Harnessing FPGA Technology for Energy-Efficient Wearable Medical DevicesElectronics10.3390/electronics1320409413:20(4094)Online publication date: 17-Oct-2024
https://doi.org/10.3390/electronics13204094
Bartzoudis NRubio Fernández JLópez-Bueno DRomán Villarroel AAntonopoulos A(2024)Agile FPGA Computing at the 5G Edge: Joint Management of Accelerated and Software Functions for Open Radio Access TechnologiesElectronics10.3390/electronics1304070113:4(701)Online publication date: 9-Feb-2024
https://doi.org/10.3390/electronics13040701
Chen KMason Nelson TKhadem AFayazi MSingapuram SDreslinski RTalati NKim HBlaauw D(2024)Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless CommunicationACM Transactions on Reconfigurable Technology and Systems10.1145/369588017:4(1-32)Online publication date: 18-Sep-2024
https://dl.acm.org/doi/10.1145/3695880
Hutto KMooney V(2024)Implementing Privacy Homomorphism with Random Encoding and Computation Controlled by a Remote Secure ServerACM Transactions on Embedded Computing Systems10.1145/365161724:2(1-27)Online publication date: 8-Mar-2024
https://dl.acm.org/doi/10.1145/3651617
Kornaros GLeivadaros SKolimbianakis F(2024)Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial ReconfigurationACM Transactions on Embedded Computing Systems10.1145/364382523:2(1-25)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1145/3643825
Xu YZhao ZXiao YYu TMulaosmanovic HKleimaier DDuenkel SBeyer SGong XJoshi RHu XWen SRios ALekkala KItti LHoman EGeorge SNarayanan VNi K(2024)Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machinesScience Advances10.1126/sciadv.adk152510:3Online publication date: 19-Jan-2024
https://doi.org/10.1126/sciadv.adk1525
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents