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Bobin Deng
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2020 – today
- 2024
- [j5]Bobin Deng, Bhargava Nadendla, Kun Suo, Chloe Yixin Xie, Dan Chia-Tien Lo:
Fixed-point Encoding and Architecture Exploration for Residue Number Systems. ACM Trans. Archit. Code Optim. 21(3): 53:1-53:27 (2024) - [c13]Nobel Dhar, Bobin Deng, Dan C. Lo, Xiaofeng Wu, Liang Zhao, Kun Suo:
An Empirical Analysis and Resource Footprint Study of Deploying Large Language Models on Edge Devices. ACM Southeast Regional Conference 2024: 69-76 - [c12]Md. Romyull Islam, Long Vu, Nobel Dhar, Bobin Deng, Kun Suo:
Building a Resilient and Sustainable Grid: A Study of Challenges and Opportunities in AI for Smart Virtual Power Plants. ACM Southeast Regional Conference 2024: 95-103 - [c11]Yi Gu, Liang Zhao, Bobin Deng, Shaoen Wu:
Evaluation of Thermal Stress on IoT-based Federated Learning. ACM Southeast Regional Conference 2024: 291-296 - [i2]Manh V. Nguyen, Liang Zhao, Bobin Deng, William Severa, Honghui Xu, Shaoen Wu:
The Robustness of Spiking Neural Networks in Communication and its Application towards Network Efficiency in Federated Learning. CoRR abs/2409.12769 (2024) - 2023
- [c10]Dan Chia-Tien Lo, Bobin Deng, Yong Shi:
Deep Machine Learning on Segmenting and Classifying Crop Images Taken by Unmanned Aerial Vehicle. IEEE Big Data 2023: 3470-3478 - [c9]Bobin Deng, Xinyue Zhang, Dan Chia-Tien Lo:
Serverless-DFS: Serverless Federated Learning with Dynamic Forest Strategy. ICNCC 2023: 168-174 - 2022
- [j4]Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers 71(3): 613-627 (2022)
2010 – 2019
- 2018
- [j3]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank:
Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. 15(1): 8:1-8:27 (2018) - [c8]Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank:
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA 2018: 696-709 - 2016
- [c7]Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte:
Energy efficiency limits of logic and memory. ICRC 2016: 1-8 - [c6]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC 2016: 1-8 - [i1]Sriseshan Srikanth, Bobin Deng, Thomas M. Conte:
A Brief Survey of Non-Residue Based Computational Error Correction. CoRR abs/1611.03099 (2016) - 2014
- [j2]Gongming Li, Hong An, Qi Li, Bobin Deng, Wenbo Dai:
Efficient execution of speculative threads and transactions with hardware transactional memory. Future Gener. Comput. Syst. 30: 242-253 (2014) - 2012
- [j1]Qi Li, Hong An, Wenbo Dai, Gongming Li, Bobin Deng, Yu Liu, Xiaomei Li, Shilei Wu:
Priority-based squash reducing methods in thread level speculation. Int. J. Inf. Technol. Commun. Convergence 2(2): 138-154 (2012) - [c5]Mengjie Mao, Hong An, Tao Sun, Qi Li, Bobin Deng, Xuechao Wei, Junrui Zhou:
Distributed Control Independence for Composable Multi-processors. ACIS-ICIS 2012: 124-129 - [c4]Bobin Deng, Hong An, Qi Li, Gongming Li, Mengjie Mao:
Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor. ACIS-ICIS 2012: 130-135 - [c3]Gongming Li, Hong An, Qi Li, Bobin Deng, Wenbo Dai:
SeTM: Efficient Execution of Speculative Threads with Hardware Transactional Memory. ICPADS 2012: 522-531 - [c2]Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han:
Distributed replay protocol for distributed uniprocessors. ICS 2012: 3-14 - 2011
- [c1]Wenbo Dai, Hong An, Qi Li, Gongming Li, Bobin Deng, Shilei Wu, Xiaomei Li, Yu Liu:
A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors. ISPA 2011: 87-92
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