research-article

Open access

Extending Moore’s Law via Computationally Error-Tolerant Computing

Authors:

Sriseshan Srikanth,

Thomas M. Conte,

Erik Debenedictis,

Michael P. FrankAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 1

Article No.: 8, Pages 1 - 27

https://doi.org/10.1145/3177837

Published: 22 March 2018 Publication History

Abstract

Dennard scaling has ended. Lowering the voltage supply (V_dd) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower V_dd in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower V_dd. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. From the simulation results, this RRNS system can reduce the energy-delay-product by about 3× for multiplication intensive workloads and by about 2× in general, when compared to a non-error-correcting binary core.

References

[1]

Daniel Anderson. 2014. Design and implementation of an instruction set architecture and an instruction execution unit for the REZ9 coprocessor system. M.S. thesis, University of Nevada Las Vegas (2014).

[2]

Todd M. Austin. 1999. DIVA: A reliable substrate for deep submicron microarchitecture design. In Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO-32). IEEE, 196--207.

Digital Library

[3]

Jean-Claude Bajard, Julien Eynard, and Nabil Merkiche. 2016. Multi-fault attack detection for RNS cryptographic architecture. In Proceedings of the 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH’16). IEEE, 16--23.

[4]

J.-C. Bajard and Laurent Imbert. 2004. A full RNS implementation of RSA. IEEE Trans. Comput. 53, 6 (2004), 769--774.

Digital Library

[5]

Ferruccio Barsi and Piero Maestrini. 1974. Error detection and correction by product codes in residue number systems. IEEE Trans. Comput. 100, 9 (1974), 915--924.

Digital Library

[6]

David T. Brown. 1960. Error detecting and correcting binary codes for arithmetic operations. IRE Trans. Electr. Comput. 3 (1960), 333--337.

[7]

Y. G. C. Cardarilli, M. Re, and R. Lojacono. 1998. RNS-to-binary conversion for efficient VLSI implementation. In IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 45, 6 (1998), 667--669.

[8]

Chip-Hong Chang, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, and Tian Fatt Tay. 2015. Residue number systems: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications. IEEE Circ. Syst. Mag. 15, 4 (2015), 26--44.

[9]

Jen-Shiun Chiang and Mi Lu. 1991. Floating-point numbers in residue number systems. Comput. Math. Appl. 22, 10 (1991), 127--140.

[10]

Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, and Stanislaw J. Piestrak. 2009. Exploiting residue number system for power-efficient digital signal processing in embedded processors. In Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. ACM, 19--28.

Digital Library

[11]

B. Deng, S. Srikanth, E. R. Hein, P. G. Rabbat, T. M. Conte, E. DeBenedictis, and J. Cook. 2016. Computationally-redundant energy-efficient processing for y’all (CREEPY). In Proceedings of the IEEE International Conference on Rebooting Computing (ICRC’16). 1--8.

[12]

R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc. 1974. Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circ. 9, 5 (Oct. 1974), 256--268.

[13]

Elio D. Di Claudio, Gianni Orlandi, and Francesco Piazza. 1993. A systolic redundant residue arithmetic error correction circuit. IEEE Trans. Comput. 42, 4 (1993), 427--432.

Digital Library

[14]

Elio D. Di Claudio, Francesco Piazza, and Gianni Orlandi. 1995. Fast combinatorial RNS processors for DSP applications. IEEE Trans. Comput. 44, 5 (1995), 624--633.

Digital Library

[15]

Shlomi Dolev, Sergey Frenkel, Dan E. Tamir, and Vladimir Sinelnikov. 2013. Preserving hamming distance in arithmetic and logical operations. J. Electr. Test. 29, 6 (2013), 903--907.

Digital Library

[16]

Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and others. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36). IEEE, 7--18.

Digital Library

[17]

M. Etzel and W. Jenkins. 1980. Redundant residue number systems for error detection and correction in digital filters. IEEE Trans. Acoust. Speech Sign. Process. 28, 5 (1980), 538--545.

[18]

Christof Fetzer, Ute Schiffel, and Martin Süßkraut. 2009. AN-encoding compiler: Building safety-critical systems with commodity hardware. In Proceedings of the International Conference on Computer Safety, Reliability, and Security. Springer, 283--296.

Digital Library

[19]

P. Forin. 1989. Vital coded microprocessor principles and application for various transit systems. In IFAC/IFIP/IFORS Symposium. 79--84.

[20]

Swaroop Ghosh, Patrick Ndai, and Kaushik Roy. 2008. A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking. In Proceedings of the Design, Automation and Test in Europe (DATE’08). IEEE, 366--371.

Digital Library

[21]

Vik Tor Goh and Mohammad Umar Siddiqi. 2008. Multiple error detection and correction based on redundant residue number systems. In IEEE Transactions on Communications 56, 3 (2008), 325--330.

[22]

Oded Goldreich, Dana Ron, and Madhu Sudan. 1999. Chinese remaindering with errors. In Proceedings of the 31st Annual ACM Symposium on Theory of Computing. ACM, 225--234.

Digital Library

[23]

Meeta S. Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, and David Brooks. 2008. DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors. In Proceedings of the IEEE 14th International Symposium on High Performance Computer Architecture (HPCA’08). IEEE, 381--392.

[24]

Nor Zaidi Haron and Said Hamdioui. 2011. Redundant residue number system code for fault-tolerant hybrid memories. ACM J. Emerg. Technol. Comput. Syst. 7, 1 (2011), 4.

Digital Library

[25]

C. W. Hastings. 1966. Automatic detection and correction of errors in digital computers using residue arithmetic. In Proceedings of the Region Six Annual Conference. IEEE, 429--464.

[26]

Yuang-Ming Hsu and E. E. Swartzlander. 1992. Time redundant error correcting adders and multipliers. In Proceedings of the 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE, 247--256.

[27]

Yuang-Ming Hsu and E. E. Swartzlander. 1992. Time redundant error correcting adders and multipliers. In Proceedings of the International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE, 247--256.

[28]

Ching Yu Hung and Behrooz Parhami. 1994. Fast RNS division algorithms for fixed divisors with application to RSA encryption. Inform. Process. Lett. 51, 4 (1994), 163--169.

Digital Library

[29]

IBM. 2014. IBM power system E880 server, an IBM POWER8 technology-based system, addresses the requirements of an industry-leading enterprise class system. IBM Europe, Middle East, and Africa Hardware Announcement ZG14-0262.

[30]

Barry W. Johnson, James H. Aylor, and Haytham H. Hana. 1988. Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder. IEEE J. Solid-State Circ. 23, 1 (1988), 208--215.

[31]

Barry W. Johnson, James H. Aylor, and Haytham H. Hana. 1988. Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder. J. Solid-State Circ. 23, 1 (1988), 208--215.

[32]

Rajendra S. Katti. 1996. A new residue arithmetic error correction scheme. IEEE Trans. Comput. 45, 1 (1996), 13--19.

Digital Library

[33]

Osnat Keren, Ilya Levin, Vladimir Ostrovsky, and Beni Abramov. 2008. Arbitrary error detection in combinational circuits by using partitioning. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFTVS’08). IEEE, 361--369.

Digital Library

[34]

Asif Islam Khan, Korok Chatterjee, Juan Pablo Duarte, Zhongyuan Lu, Angada Sachid, Sourabh Khandelwal, Ramamoorthy Ramesh, Chenming Hu, and Sayeef Salahuddin. 2016. Negative capacitance in short-channel FinFETs externally connected to an epitaxial ferroelectric capacitor. IEEE Electr. Dev. Lett. 37, 1 (2016), 111--114.

[35]

Asif Islam Khan and Sayeef Salahuddin. 2015. Extending CMOS with negative capacitance. In CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, T. King Liu and K. Kuhn (Eds.). Cambridge: Cambridge University Press, 56--76.

[36]

Asif I. Khan, Chun W. Yeung, Chenming Hu, and Sayeef Salahuddin. 2011. Ferroelectric negative capacitance MOSFET: Capacitance tuning 8 antiferroelectric operation. In Proceedings of the 2011 IEEE International Electron Devices Meeting (IEDM’11). IEEE, 11--3.

[37]

E. V. Krekhov, Al-r A. Pavlov, A. A. Pavlov, P. A. Pavlov, D. V. Smirnov, A. N. Tsar’kov, P. A. Chistopol’skii, A. V. Shandrikov, B. A. Sharikov, and D. A. Yakimov. 2008. A method of monitoring execution of arithmetic operations on computers in computerized monitoring and measuring systems. Meas. Techn. 51, 3 (2008), 237--241.

[38]

Hari Krishna, Bal Krishna, Kuo-Yu Lin, and Jenn-Dong Sun. 1994. Computational Number Theory and Digital Signal Processing: Fast Algorithms and Error Control Techniques. Vol. 6. CRC Press.

Digital Library

[39]

Hari Krishna, K.-Y. Lin, and J.-D. Sun. 1992. A coding theory approach to error control in redundant residue number systems. I. Theory and single error correction. IEEE Trans. Circ. Syst. II: Analog Dig. Sign. Process. 39, 1 (1992), 8--17.

[40]

Daniel Lipetz and Eric Schwarz. Self checking in current floating-point units. In Proceedings of the 2011 IEEE 20th Symposium on Computer Arithmetic (ARITH’11). IEEE Computer Society, Washington, DC, 73--76.

Digital Library

[41]

Chao-Kai Liu. 1972. Error-correcting-codes in Computer Arithmetic. Technical Report. DTIC Document.

[42]

Hao-Yung Lo and Ting-Wei Lin. 2013. Parallel algorithms for residue scaling and error correction in residue arithmetic. Wireless Eng. Technol. 4, 04 (2013), 198.

[43]

Florence Jessie MacWilliams and Neil James Alexander Sloane. 1977. The Theory of Error-correcting Codes. Elsevier.

[44]

Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, and M. Gossel. 2005. New self-checking output-duplicated booth multiplier with high fault coverage for soft errors. In Proceedings of the 14th Asian Test Symposium, 2005. IEEE, 76--81.

Digital Library

[45]

J. Mathew, S. Banerjee, P. Mahesh, D. K. Pradhan, A. M. Jabir, and S. P. Mohanty. 2010. Multiple bit error detection and correction in GF arithmetic circuits. In Proceedings of the 2010 International Symposium on Electronic System Design (ISED’10). IEEE, 101--106.

Digital Library

[46]

A. McMenamin. 2013. The end of dennard scaling.

[47]

Elias Mizan, Tileli Amimeur, and Margarida F. Jacome. 2007. Self-imposed temporal redundancy: An efficient technique to enhance the reliability of pipelined functional units. In Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’07). IEEE, 45--53.

[48]

Michael Nicolaidis. 2003. Carry checking/parity prediction adders and ALUs. IEEE Trans. VLSI Syst. 11, 1 (2003), 121--128.

Digital Library

[49]

Michael Nicolaidis and Hakim Bederr. 1994. Efficient implementations of self-checking multiply and divide arrays. In Proceedings of the European Design and Test Conference (EDAC’94). IEEE, 574--579.

[50]

Michael Nicolaidis and R. O. Duarte. 1998. Design of fault-secure parity-prediction booth multipliers. In Proceedings of the European Design, Automation and Test Conference. IEEE, 7--14.

Digital Library

[51]

Eric B. Olsen. 2015. Introduction of the residue number arithmetic logic unit with brief computational complexity analysis (Rez-9 soft processor). Whitepaper, Digital System Research (2015).

[52]

Amos Omondi and Benjamin Premkumar. Residue Number Systems: Theory and Implementation. Imperial College Press.

Digital Library

[53]

Glenn A. Orton, Lloyd E. Peppard, and Stafford E. Tavares. 1992. New fault tolerant techniques for residue number systems. IEEE Trans. Comput. 41, 11 (1992), 1453--1464.

Digital Library

[54]

Janak H. Patel and Leona Y. Fung. 1982. Concurrent error detection in ALU’s by recomputing with shifted operands. IEEE Trans. Comput. 31, 7 (1982), 589--595.

Digital Library

[55]

Song Peng and Rajit Manohar. 2005. Fault tolerant asynchronous adder through dynamic self-reconfiguration. In Proceedings of the 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD’05). IEEE, 171--178.

Digital Library

[56]

Song Peng and Rajit Manohar. 2005. Fault tolerant asynchronous adder through dynamic self-reconfiguration. In Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD’05). IEEE, 171--178.

Digital Library

[57]

A. P. Preethy and D. Radhakrishnan. 1999. A 36-bit balanced moduli MAC architecture. In Proceedings of the 42nd Midwest Symposium on Circuits and Systems, Vol. 1. IEEE, 380--383.

[58]

A. P. Preethy and D. Radhakrishnan. 2000. RNS-based logarithmic adder. IEEE Proc. Comput. Dig. Techn. 147, 4 (2000), 283--287.

[59]

Vijaya Ramachandran. 1983. Single residue error correction in residue number systems. IEEE Trans. Comput. 32, 5 (1983), 504--507.

Digital Library

[60]

J. Ramirez, A. Garcia, S. Lopez-Buedo, and A. Lloris. 2002. RNS-enabled digital signal processor design. Electron. Lett. 38, 6 (2002), 266--268.

[61]

Thammavarapu R. N. Rao. 1970. Biresidue error-correcting codes for computer arithmetic. IEEE Trans. Comput. 100, 5 (1970), 398--402.

Digital Library

[62]

Wenjing Rao and Alex Orailoglu. 2008. Towards fault tolerant parallel prefix adders in nanoelectronic systems. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’08). IEEE, 360--365.

Digital Library

[63]

Wenjing Rao, Alex Orailoglu, and Ramesh Karri. 2006. Fault identification in reconfigurable carry lookahead adders targeting nanoelectronic fabrics. In Proceedings of the 11th IEEE EuropeanTest Symposium (ETS’06). IEEE, 63--68.

Digital Library

[64]

Stefan Rusu. 2010. Multi-domain processors design overview. ISCA Tutorial on Multi-domain Processors: Challenges, Design Methods, and Recent Developments (June 2010). Saint Malo, France.

[65]

Sayeef Salahuddin and Supriyo Datta. 2008. Can the subthreshold swing in a classical FET be lowered below 60 mV/decade? In Proceedings of the IEEE International Electron Devices Meeting (IEDM’08). IEEE, 1--4.

[66]

Ute Schiffel, André Schmitt, Martin Süßkraut, and Christof Fetzer. 2010. ANB-and ANBDmem-encoding: Detecting hardware errors in software. In Proceedings of the International Conference on Computer Safety, Reliability, and Security. Springer, 169--182.

Digital Library

[67]

Avik Sengupta and Balasubramaniam Natarajan. 2013. Performance of systematic RRNS based space-time block codes with probability-aware adaptive demapping. IEEE Trans. Wireless Commun. 12, 5 (2013), 2458--2469.

[68]

Y. Shimazaki, R. Zlatanovici, and B. Nikolic. 2004. A shared-well dual-supply-voltage 64-bit ALU. J. Solid-State Circ. 39, 3 (2004), 494--500.

[69]

Sriseshan Srikanth, Bobin Deng, and Thomas M. Conte. 2016. A brief survey of non-residue based computational error correction. arXiv Preprint arXiv:1611.03099 (2016).

[70]

S. Srikanth, P. G. Rabbat, E. R. Hein, B. Deng, T. M. Conte, E. DeBenedictis, J. Cook, and M Frank. Memory system design for ultra low power, computationally error resilient processor microarchitectures (unpublished).

[71]

C.-C. Su and H.-Y. Lo. 1990. An algorithm for scaling and single residue error correction in residue number systems. IEEE Trans. Comput. 39, 8 (1990), 1053--1064.

Digital Library

[72]

J.-D. Sun and Hari Krishna. 1992. A coding theory approach to error control in redundant residue number systems. II. Multiple error detection and correction. IEEE Trans. Circ. Syst. II: Analog Dig. Sign. Process. 39, 1 (1992), 18--34.

[73]

J.-D. Sun, Hari Krishna, and K. Y. Lin. 1992. A superfast algorithm for single-error correction in RRNS and hardware implementation. In Proceedings of the 1992 IEEE International Symposium on Circuits and Systems (ISCAS’92), Vol. 2. IEEE, 795--798.

[74]

Yan Sun, Minxuan Zhang, Shaoqing Li, and Yali Zhao. 2010. Cost effective soft error mitigation for parallel adders by exploiting inherent redundancy. In Proceedings of the 2010 IEEE International Conference on IC Design and Technology (ICICDT’10). IEEE, 224--227.

[75]

Andraos Sweidan and Ahmad A Hiasat. 2001. On the theory of error control based on moduli with common factors. Reliable Comput. 7, 3 (2001), 209--218.

[76]

Nicholas S. Szabo and Richard I. Tanaka. 1967. Residue Arithmetic and its Applications to Computer Technology. McGraw--Hill.

[77]

J. Tan and O. Rosen. 2004. Process for determining competing cause event probability and/or system availability during the simultaneous occurrence of multiple events. (Apr. 22, 2004). US Patent App. 10/272,156.

[78]

Yangyang Tang, Emmanuel Boutillon, Christophe Jégo, and Michel Jézéquel. 2010. A new single-error correction scheme based on self-diagnosis residue number arithmetic. In Proceedings of the 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP’10). IEEE, 27--33.

[79]

Thian Fatt Tay and Chip-Hong Chang. 2014. A new algorithm for single residue digit error correction in redundant residue number system. In Proceedings of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS’14). IEEE, 1748--1751.

[80]

Thian Fatt Tay and Chip-Hong Chang. 2016. A non-iterative multiple residue digit error detection and correction algorithm in RRNS. IEEE Trans. Comput. 65, 2 (2016), 396--408.

Digital Library

[81]

T. N. Theis. 2012. (keynote) in quest of a fast, low-voltage digital switch. ECS Trans. 45, 6 (2012), 3--11.

[82]

T. N. Theis and P. M. Solomon. 2010. In quest of the next switch: Prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor. Proc. IEEE 98, 12 (Dec. 2010), 2005--2014.

[83]

Mojtaba Valinataj and Saeed Safari. 2007. Fault tolerant arithmetic operations with multiple error detection and correction. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07). IEEE, 188--196.

Digital Library

[84]

Dilip P. Vasudevan and Parag K. Lala. 2005. A technique for modular design of self-checking carry-select adder. In Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05). IEEE, 325--333.

Digital Library

[85]

Dilip P. Vasudevan, Parag K. Lala, and James Patrick Parkerson. 2007. Self-checking carry-select adder design based on two-rail encoding. IEEE Trans. Circ. Syst. I: Regul. Pap. 54, 12 (2007), 2696--2705.

[86]

John Von Neumann. 1956. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In Automata Studies. Princeton University Press, 43--98.

[87]

E. George Walters III, Mark G. Arnold, and Michael J. Schulte. 2003. Using truncated multipliers in DCT and IDCT hardware accelerators. In Proceedings of SPIE’s 48th Annual Meeting on Optical Science and Technology. International Society for Optics and Photonics, 573--584.

[88]

Ute Wappler and Christof Fetzer. 2007. Hardware failure virtualization via software encoded processing. In Proceedings of the 2007 5th IEEE International Conference on Industrial Informatics, Vol. 2. IEEE, 977--982.

[89]

R. W. Watson. 1965. Error detection and correction and other residue interacting operations in a residue redundant number system. University of California, Berkeley.

[90]

Richard W. Watson and Charles W. Hastings. 1966. Self-checked computation using residue arithmetic. Proc. IEEE 54, 12 (1966), 1920--1931.

[91]

Hanshen Xiao, Hari Krishna Garg, Jianhao Hu, and Guoqiang Xiao. 2016. New error control algorithms for residue number system codes. ETRI J. 38, 2 (2016), 326--336.

[92]

Li Xiao and Xiang-Gen Xia. 2015. Error correction in polynomial remainder codes with non-pairwise coprime moduli and robust Chinese remainder theorem for polynomials. IEEE Trans. Commun. 63, 3 (2015), 605--616.

[93]

S. S.-S. Yau and Yu-Cheng Liu. 1973. Error correction in redundant residue number systems. IEEE Trans. Comput. 100, 1 (1973), 5--11.

Digital Library

[94]

Sung-Ming Yen, Seungjoo Kim, Seongan Lim, and Sang-Jae Moon. 2003. RSA speedup with chinese remainder theorem immune against hardware fault cryptanalysis. IEEE Trans. Comput. 52, 4 (2003), 461--472.

Digital Library

[95]

Pengsheng Yin and Lei Li. 2013. A new algorithm for single error correction in RRNS. In Proceedings of the 2013 International Conference on Communications, Circuits and Systems (ICCCAS’13), Vol. 2. IEEE, 178--181.

Cited By

Famoori FMolahosseini AZarandi A(2023)DNA Arithmetic With Error CorrectionIEEE Transactions on NanoBioscience10.1109/TNB.2022.318983322:2(329-336)Online publication date: Apr-2023
https://doi.org/10.1109/TNB.2022.3189833
Conte T(2023)Status Update on the IEEE Rebooting Computing Initiative2023 IEEE John Vincent Atanasoff International Symposium on Modern Computing (JVA)10.1109/JVA60410.2023.00012(9-13)Online publication date: 5-Jul-2023
https://doi.org/10.1109/JVA60410.2023.00012
Deng BSrikanth SJain AConte TDebenedictis ECook J(2022)Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number SystemsIEEE Transactions on Computers10.1109/TC.2021.305575471:3(613-627)Online publication date: 1-Mar-2022
https://doi.org/10.1109/TC.2021.3055754
Show More Cited By

Index Terms

Extending Moore’s Law via Computationally Error-Tolerant Computing
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks

Recommendations

PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees
Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative Computing Systems

With increasing technology scaling and design complexity there are increasing threats from device and circuit failures. This is expected to worsen with post-CMOS devices. Current error-resilient solutions ensure reliability of circuits through ...
A low-cost, systematic methodology for soft error robustness of logic circuits

Due to current technology scaling trends such as shrinking feature sizes and decreasing supply voltages, circuit reliability is becoming more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern ...
Fault Tolerant Single Error Correction Encoders

Soft errors are an important issue for circuit reliability. To mitigate their effects on the system functionality, different techniques are used. In many cases Error Correcting Codes (ECC) are used to protect circuits. Single Error Correction (SEC) ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 15, Issue 1

March 2018

401 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/3199680

Editor:
Koen De Bosschere
Ghent University

Issue’s Table of Contents

Copyright © 2018 ACM.

© 2018 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of the United States government. As such, the United States Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 March 2018

Accepted: 01 December 2017

Revised: 01 November 2017

Received: 01 June 2017

Published in TACO Volume 15, Issue 1

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

Laboratory-Directed Research and Development (LDRD) Project
National Technology and Engineering Solutions of Sandia, LLC.
Honeywell International, Inc.
U.S. Department of Energy's National Nuclear Security Administration

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
813
Total Downloads

Downloads (Last 12 months)77
Downloads (Last 6 weeks)11

Reflects downloads up to 26 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

Famoori FMolahosseini AZarandi A(2023)DNA Arithmetic With Error CorrectionIEEE Transactions on NanoBioscience10.1109/TNB.2022.318983322:2(329-336)Online publication date: Apr-2023
https://doi.org/10.1109/TNB.2022.3189833
Conte T(2023)Status Update on the IEEE Rebooting Computing Initiative2023 IEEE John Vincent Atanasoff International Symposium on Modern Computing (JVA)10.1109/JVA60410.2023.00012(9-13)Online publication date: 5-Jul-2023
https://doi.org/10.1109/JVA60410.2023.00012
Deng BSrikanth SJain AConte TDebenedictis ECook J(2022)Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number SystemsIEEE Transactions on Computers10.1109/TC.2021.305575471:3(613-627)Online publication date: 1-Mar-2022
https://doi.org/10.1109/TC.2021.3055754
Sousa L(2021)Nonconventional Computer Arithmetic Circuits, Systems and ApplicationsIEEE Circuits and Systems Magazine10.1109/MCAS.2020.302742521:1(6-40)Online publication date: Sep-2022
https://doi.org/10.1109/MCAS.2020.3027425
Olsen E(2020)Continuous Error Detection and Correction of Arithmetic in a Complement RRNS2020 10th Annual Computing and Communication Workshop and Conference (CCWC)10.1109/CCWC47524.2020.9031218(0009-0017)Online publication date: Jan-2020
https://doi.org/10.1109/CCWC47524.2020.9031218
Mazuecos Pérez MSeiler NBederián CWolovick NVega A(2019)Power Efficiency Analysis of a Deep Learning Workload on an IBM “Minsky” PlatformHigh Performance Computing10.1007/978-3-030-16205-4_19(255-262)Online publication date: 31-Mar-2019
https://doi.org/10.1007/978-3-030-16205-4_19

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents