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ORCIDDmitrij Kissler
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2010 – 2019
- 2012
[b1]Dmitrij Kissler:
Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal Processing. University of Erlangen-Nuremberg, 2012- 2011
- [j4]Dmitrij Kissler, D. Gran, Zoran Salcic
, Frank Hannig, Jürgen Teich:
Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. IEEE Embed. Syst. Lett. 3(2): 58-61 (2011) - [j3]Dmitrij Kissler, Frank Hannig, Jürgen Teich:
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. 7(1): 29-40 (2011)
2000 – 2009
- 2009
- [j2]Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich:
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electron. 5(1): 96-105 (2009) - [j1]Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier:
A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems 33(1): 53-62 (2009) - 2008
- [c11]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Coarse-grained reconfiguration. FPL 2008: 349 - [c10]Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich:
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317 - 2007
- [c9]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282 - [c8]Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24 - [c7]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - [c6]Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich:
Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80 - 2006
- [c5]Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195 - [c4]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
A highly parameterizable parallel processor array architecture. FPT 2006: 105-112 - [c3]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC 2006: 1-4 - [c2]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker:
An Architecture Description Language for Massively Parallel Processor Architectures. MBMV 2006: 11-20 - [c1]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37
Coauthor Index
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