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ORCIDSamuel Naffziger
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- affiliation: AMD, Fort Collins, CO, USA
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2020 – today
- 2024
[c23]Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, Eric Chapman, Raja Swaminathan:
Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. ISCA 2024: 876-889- [c22]Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan:
AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c21]Lisa Su, Sam Naffziger:
Innovation For the Next Decade of Compute Efficiency. ISSCC 2023: 8-12 - 2022
- [c20]John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger:
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. ISSCC 2022: 428-429 - 2021
- [c19]Gabriel H. Loh, Samuel Naffziger, Kevin Lepak:
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. DATE 2021: 142-145 - [c18]Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White:
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. ISCA 2021: 57-70 - [c17]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538 - [c16]Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger:
A New Era of Tailored Computing. VLSI Circuits 2021: 1-2 - 2020
- [c15]Samuel Naffziger, Kevin Lepak, Milam Paraschou, Mahesh Subramony:
2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. ISSCC 2020: 44-45 - [c14]Sal Dasgupta, Teja Singh, Ashish Jain, Samuel Naffziger, Deepesh John, Chetan Bisht, Pradeep Jayaraman:
8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs. ISSCC 2020: 150-152
2010 – 2019
- 2019
- [j16]Thomas Burd
, Noah Beck, Sean White, Milam Paraschou, Nathan Kalyanasundharam, Gregg Donley, Alan Smith, Larry Hewitt, Samuel Naffziger:
"Zeppelin": An SoC for Multichip Architectures. IEEE J. Solid State Circuits 54(1): 133-143 (2019) - 2018
- [j15]Teja Singh, Alex Schaefer, Sundar Rangarajan, Deepesh John, Carson Henrion, Russell Schreiber, Miguel Rodriguez, Stephen Kosonocky, Samuel Naffziger, Amy Novak:
Zen: An Energy-Efficient High-Performance × 86 Core. IEEE J. Solid State Circuits 53(1): 102-114 (2018) - [c13]Noah Beck, Sean White, Milam Paraschou, Samuel Naffziger:
'Zeppelin': An SoC for multichip architectures. ISSCC 2018: 40-42 - 2017
- [j14]Sriram Sundaram, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy:
Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. IEEE J. Solid State Circuits 52(1): 89-97 (2017) - 2016
- [j13]Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox:
Carrizo: A High Performance, Energy Efficient 28 nm APU. IEEE J. Solid State Circuits 51(1): 105-116 (2016) - [j12]Guhan Krishnan, Dan Bouvier, Samuel Naffziger:
Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit. IEEE Micro 36(2): 22-33 (2016) - [c12]Sriram Sundaram, Warren He, Sriram Sambamurthy, Aaron Grenat, Steven Liepe, Samuel Naffziger:
Unified Power Frequency Model Framework. ISLPED 2016: 174-179 - [c11]Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger:
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. ISSCC 2016: 74-75 - [c10]Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger:
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. VLSID 2016: 565-566 - 2015
- [j11]Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White:
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. IEEE J. Solid State Circuits 50(1): 24-34 (2015) - [j10]Samuel Naffziger, Guri Sohi:
Hot Chips 26 [Guest editors' introduction]. IEEE Micro 35(2): 4-5 (2015) - [c9]Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White:
4.8 A 28nm x86 APU optimized for power and area efficiency. ISSCC 2015: 1-3 - 2014
- [c8]William Lloyd Bircher, Sam Naffziger:
AMD SOC power management: Improving performance/watt using run-time feedback. CICC 2014: 1-4 - [c7]Samuel Naffziger, Guri Sohi:
Welcome program chairs. Hot Chips Symposium 2014: 1-2 - [c6]Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger:
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. ISSCC 2014: 106-107 - 2013
- [j9]Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger:
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits 48(1): 140-149 (2013) - 2012
- [j8]Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh:
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. IEEE J. Solid State Circuits 47(1): 164-176 (2012) - [c5]Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger:
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. CICC 2012: 1-4 - [c4]Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger:
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC 2012: 68-70 - 2011
- [j7]Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Amy Novak, Sam Naffziger:
An x86-64 Core in 32 nm SOI CMOS. IEEE J. Solid State Circuits 46(1): 162-172 (2011) - [c3]Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox:
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. ISSCC 2011: 78-80 - 2010
- [c2]Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, Amy Novak, Sam Naffziger:
An x86-64 core implemented in 32nm SOI CMOS. ISSCC 2010: 106-107 - [c1]Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon:
A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency. ISSCC 2010: 210-211
2000 – 2009
- 2006
- [j6]Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz:
The implementation of a 2-core, multi-threaded itanium family processor. IEEE J. Solid State Circuits 41(1): 197-209 (2006) - [j5]Tim C. Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella:
A 90-nm variable frequency clock system for a power-managed itanium architecture processor. IEEE J. Solid State Circuits 41(1): 218-228 (2006) - [j4]Rich McGowen, Christopher Poirier, Chris Bostak, Jim Ignowski, Mark Millican, Warren H. Parks, Samuel Naffziger:
Power and temperature control on a 90-nm Itanium family processor. IEEE J. Solid State Circuits 41(1): 229-237 (2006) - 2003
- [j3]David M. Harris, Sam Naffziger:
Correction to "statistical clock skew modeling with data delay variations". IEEE Trans. Very Large Scale Integr. Syst. 11(2): 295-296 (2003) - 2002
- [j2]Samuel D. Naffziger, Glenn Colón-Bonet, Timothy C. Fischer, Reid J. Riedlinger, Thomas J. Sullivan, Tom Grutkowski:
The implementation of the Itanium 2 microprocessor. IEEE J. Solid State Circuits 37(11): 1448-1460 (2002) - 2001
- [j1]David M. Harris, Sam Naffziger:
Statistical clock skew modeling with data delay variations. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 888-898 (2001)
Coauthor Index
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