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ORCIDIEEE Journal of Solid-State Circuits, Volume 50
Volume 50, Number 1, January 2015
- Michael P. Flynn:
New Associate Editors. 3 - Vivek De, Stephen Kosonocky, Jonathan Chang, Yogesh K. Ramadass, David Stoppa:
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions. 4-9 - Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. 10-23 - Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White:
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. 24-34 - Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li
, Sujal Vora, Raj Varada, Eddie Wang:
A 22 nm 15-Core Enterprise Xeon® Processor Family. 35-48 - Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, Mark Neidengard, Anant Deval, Ashish Khanna, Nasirul Chowdhury, Ravi Rajwar, Timothy M. Wilson, Rajesh Kumar:
Haswell: A Family of IA 22 nm Processors. 49-58 - Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. 59-67 - Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. 68-80 - Martin Saint-Laurent, Paul Bassett, Ken Lin, Baker Mohammad, Yuhe Wang, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Marzio Pedrali-Noy, Willie Anderson:
A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications. 81-91 - Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. 92-101 - Michael Price, James R. Glass, Anantha P. Chandrakasan:
A 6 mW, 5, 000-Word Real-Time Speech Recognizer Using WFST Models. 102-112 - Gyeonghoon Kim, Kyuho Jason Lee, Youchang Kim, Seongwook Park, Injoon Hong, Kyeongryeol Bong, Hoi-Jun Yoo:
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications. 113-124 - Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart:
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. 125-136 - Fang-Li Yuan, Cheng C. Wang, Tsung-Han Yu, Dejan Markovic:
A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing. 137-149 - Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang:
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. 150-157 - Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park, Yongho Kim, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi, Hyo-Sig Won, Jaehong Park:
A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. 158-169 - Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang:
A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. 170-177 - Tae-Young Oh, Hoeju Chung, Jun-Young Park, Ki-Won Lee, Seung-Hoon Oh, Su-Yeon Doo, Hyoung-Joo Kim, ChangYong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, Young-Ryeol Choi, Young-Chul Cho, Yong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi:
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. 178-190 - Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jae-Hwan Kim, Jin-Hee Cho, Jaejin Lee, Jun Hyun Chun:
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits. 191-203 - Ki-Tae Park, Sangwan Nam, Dae-Han Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Minsu Kim, Hyun Wook Park, Sang-Won Shim, Kyung-Min Kang, Sang-Won Park, Kangbin Lee, Hyun-Jun Yoon, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dae-Seok Byeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Jeong-Hyuk Choi, Kinam Kim:
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. 204-213 - Marcus Yip, Rui Jin, Hideko Heidi Nakajima, Konstantina M. Stankovic, Anantha P. Chandrakasan:
A Fully-Implantable Cochlear Implant SoC With Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation. 214-229 - Nick Van Helleputte, Mario Konijnenburg, Julia Pettine, Dong-Woo Jee, Hyejung Kim, Alonso Morgado, Roland Van Wegberg, Tom Torfs, Rachit Mohan, Arjan Breeschoten, Harmke de Groot, Chris Van Hoof, Refet Firat Yazicioglu:
A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP. 230-244 - Sunjoo Hong, Kwonjoon Lee, Unsoo Ha, Hyunki Kim, Yongsu Lee, Youchang Kim, Hoi-Jun Yoo:
A 4.9 mΩ-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System. 245-257 - Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, Liam Madden:
A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters. 258-269 - Junjie Lu, Steven R. Young, Itamar Arel, Jeremy Holleman:
A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS. 270-281 - Jan Genoe, Koji Obata, Marc Ameys, Kris Myny, Tung Huei Ke, Manoj Nag, Soeren Steudel, Sarah Schols, Joris Maas, Ashutosh Tripathi, Jan-Laurens P. J. van der Steen, Tim Ellis, Gerwin H. Gelinck, Paul Heremans:
Integrated Line Driver for Digital Pulse-Width Modulation Driven AMOLED Displays on Flex. 282-290 - Samira Zali Asl, James C. Salvia, Ginel C. Hill, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, Meghan Phadke, Shouvik Mukherjee, Haechang Lee, Charles Grosjean, Paul M. Hagelin, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon:
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator. 291-302 - Cyrus S. Bamji, Patrick O'Connor, Tamer A. Elkhatib, Swati Mehta, Barry Thompson, Lawrence A. Prather, Dane Snow, Onur Can Akkaya, Andy Daniel, Andrew D. Payne, Travis Perry, Mike Fenton, Vei-Han Chan:
A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC. 303-319 - Richard J. Przybyla, Hao-Yen Tang, André Guedes, Stefon E. Shelton, David A. Horsley, Bernhard E. Boser:
3D Ultrasonic Rangefinder on a Chip. 320-334 - Masayuki Miyamoto, Mutsumi Hamaguchi, Akira Nagao:
A 143 × 81 Mutual-Capacitance Touch-Sensing Analog Front-End With Parallel Drive and Differential Sensing Architecture. 335-343 - Rikky Muller, Hanh-Phuc Le, Wen Li, Peter Ledochowitsch, Simone Gambini, Toni Björninen, Aaron C. Koralek, Jose M. Carmena, Michel M. Maharbiz, Elad Alon, Jan M. Rabaey:
A Minimally Invasive 64-Channel Wireless μECoG Implant. 344-359 - Hyung-Min Lee, Ki Yong Kwon, Wen Li, Maysam Ghovanloo:
A Power-Efficient Switched-Capacitor Stimulating System for Electrical/Optical Deep Brain Stimulation. 360-374 - Yen-Po Chen, Dongsuk Jeon, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Inhee Lee, Nicholas B. Langhals, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. 375-390
Volume 50, Number 2, February 2015
- Hyosup Won, Taehun Yoon, Jinho Han, Joon-Yeong Lee, Jong-Hyeok Yoon, Taeho Kim, Jeong-Sup Lee, Sangeun Lee, Kwangseok Han, Jinhee Lee, Jinho Park, Hyeon-Min Bae:
A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS. 399-413 - Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim:
A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement. 414-425 - Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz:
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links. 426-439 - Min Tan, Wing-Hung Ki:
A Cascode Miller-Compensated Three-Stage Amplifier With Local Impedance Attenuation for Optimized Complex-Pole Control. 440-449 - Christian Venerus, Ian Galton:
A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO. 450-463 - Youn Sung Park, Yaoyu Tao, Zhengya Zhang:
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. 464-475 - Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. 476-489 - Mohammad Hekmat, Farshid Aryanfar, Jason Wei, Vijay P. Gadde, Reza Navid:
A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators. 490-502 - Kyeongha Kwon, Jong-Hyeok Yoon, Hyeon-Min Bae:
A 6 Gb/s Transceiver With a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers. 503-514 - Jun Won Jung, Behzad Razavi:
A 25 Gb/s 5.8 mW CMOS Equalizer. 515-526 - Sandipan Kundu, Jeyanandh Paramesh:
A Compact, Supply-Voltage Scalable 45-66 GHz Baseband-Combining CMOS Phased-Array Receiver. 527-542 - Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu:
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. 543-555 - Jianxun Zhu, Harish Krishnaswamy, Peter R. Kinget:
Field-Programmable LNAs With Interferer-Reflecting Loop for Input Linearity Enhancement. 556-572 - Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee:
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. 573-585 - Hang Liu, Xi Zhu, Chirn Chye Boon, Xiaofeng He:
Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology. 586-596 - Yahya M. Tousi, Ehsan Afshari:
A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems. 597-609 - Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim:
Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing. 610-618 - Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". 619
Volume 50, Number 3, March 2015
- Aliakbar Homayoun, Behzad Razavi:
A Low-Power CMOS Receiver for 5 GHz WLAN. 630-643 - Mikko Englund, Kim B. Ostman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen:
A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS. 644-655 - Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Yu-Lun Chen, Jri Lee:
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology. 656-668 - Shuli Geng, Dang Liu, Yanfeng Li, Huiying Zhuo, Woogeun Rhee, Zhihua Wang:
A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications. 669-678 - Masoud Babaie, Robert Bogdan Staszewski:
An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability. 679-692 - Seyed Kasra Garakoui, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency. 693-703 - Erik Olieman, Anne-Johan Annema, Bram Nauta:
An Interleaved Full Nyquist High-Speed DAC Technique. 704-713 - Xinpeng Xing, Georges G. E. Gielen:
A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS. 714-723 - Zhe Hua, Hoi Lee:
A Reconfigurable Dual-Output Switched-Capacitor DC-DC Regulator With Sub-Harmonic Adaptive-On-Time Control for Low-Power Applications. 724-736 - Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. 737-748 - Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schluessler, Holger Eisenreich, René Schüffny:
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. 749-762 - Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang:
A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology. 763-775 - Woojae Lee, SeongHwan Cho:
Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance. 776-785 - Fernando Pardo, Jose Antonio Boluda, Francisco Vegara:
Selective Change Driven Vision Sensor With Continuous-Time Logarithmic Photoreceptor and Winner-Take-All Circuit for Pixel Selection. 786-798 - Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, Dror Zilberman:
Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process. 799-807 - Bum-Kyum Kim, Donggu Im, Jaeyoung Choi, Kwyro Lee:
Corrections to "A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization". 808
Volume 50, Number 4, April 2015
- Michael P. Flynn:
New Associate Editor. 811 - Jeffrey C. Gealow, Masato Motomura:
Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits. 812-813 - Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. 814-827 - Chen Sun, Michael Georgas, Jason Orcutt, Benjamin Moss, Yu-Hsin Chen, Jeffrey Shainline, Mark T. Wade, Karan Mehta, Kareem Nammari, Erman Timurdogan, Daniel L. Miller, Ofer Tehar-Zahav, Zvi Sternberg, Jonathan C. Leu, Johanna Chong, Reha Bafrali, Gurtej Sandhu, Michael Watts, Roy Meade, Milos A. Popovic, Rajeev J. Ram, Vladimir Stojanovic:
A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS. 828-844 - Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. 845-855 - Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS. 856-866 - Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. 867-881 - Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. 882-895 - Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. 896-907 - Stacy Ho, Chi-Lun Lo, Jiayun Ru, Jialin Zhao:
A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS. 908-919 - Yuan Zhou, Benwei Xu, Yun Chiu:
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. 920-931 - Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. 932-945 - Sy-Chyuan Hwu, Behzad Razavi:
An RF Receiver for Intra-Band Carrier Aggregation. 946-961 - Maryam Tabesh, Nemat Dolatsha, Amin Arbabian, Ali M. Niknejad:
A Power-Harvesting Pad-Less Millimeter-Sized Radio. 962-977 - Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices. 978-989 - Seong Joong Kim, Qadeer Khan, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu:
High Frequency Buck Converter Design Using Time-Based Control Techniques. 990-1001 - Liechao Huang, Warren Rieutort-Louis, Alexandra Gualdino, Laura Teagno, Yingzhe Hu, Joao Mouro, Josue Sanz-Robinson, James C. Sturm, Sigurd Wagner, Virginia Chu, João Pedro Conde, Naveen Verma:
A System Based on Capacitive Interfacing of CMOS With Post-Processed Thin-Film MEMS Resonators Employing Synchronous Readout for Parasitic Nulling. 1002-1015 - Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Fukashi Morishita:
A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit. 1016-1024 - Kiseok Song, Unsoo Ha, Seongwook Park, Joonsung Bae, Hoi-Jun Yoo:
An Impedance and Multi-Wavelength Near-Infrared Spectroscopy IC for Non-Invasive Blood Glucose Estimation. 1025-1037 - William Biederman, Daniel J. Yeager, Nathan Narevsky, Jaclyn Leverett, Ryan Neely, Jose M. Carmena, Elad Alon, Jan M. Rabaey:
A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation. 1038-1047 - Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy:
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. 1048-1058 - Kyuho Jason Lee, Gyeonghoon Kim, Junyoung Park, Hoi-Jun Yoo:
A Vocabulary Forest Object Matching Processor With 2.07 M-Vector/s Throughput and 13.3 nJ/Vector Per-Vector Energy for Full-HD 60 fps Video Object Recognition. 1059-1069 - Phil Knag, Jung Kuk Kim, Thomas Chen, Zhengya Zhang:
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding. 1070-1079
Volume 50, Number 5, May 2015
- Ranjit Gharpurey:
Introduction to the Special Section on the 2014 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. 1083-1084 - Venumadhav Bhagavatula, Mazhareddin Taghivand, Jacques Christophe Rudell:
A Compact 77% Fractional Bandwidth CMOS Band-Pass Distributed Amplifier With Mirror-Symmetric Norton Transforms. 1085-1093 - Song Hu, Shouhei Kousai, Jong Seok Park, Outmane Lemtiri Chlieh, Hua Wang:
Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS. 1094-1106 - Lei Ding, Joonhoi Hur, Aritra Banerjee, Rahmi Hezar, Baher Haroun:
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners. 1107-1116 - Rahmi Hezar, Lei Ding, Aritra Banerjee, Joonhoi Hur, Baher Haroun:
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications. 1117-1125 - Mustafijur Rahman, Mohammad Elbadry, Ramesh Harjani:
An IEEE 802.15.6 Standard Compliant 2.5 nJ/Bit Multiband WBAN Transmitter Using Phase Multiplexing and Injection Locking. 1126-1136 - Anders Nejdel, Henrik Sjöland, Markus Törmänen:
A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching. 1137-1147 - Hajir Hedayati, Wing-Fat Andy Lau, Namsoo Kim, Vladimir Aparin, Kamran Entesari:
A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS. 1148-1164 - Nitz Saputra, John R. Long:
A Fully Integrated Wideband FM Transceiver for Low Data Rate Autonomous Systems. 1165-1175 - Tong Zhang, Apsara Ravish Suvarna, Venumadhav Bhagavatula, Jacques Christophe Rudell:
An Integrated CMOS Passive Self-Interference Mitigation Technique for FDD Radios. 1176-1188 - Dong Yang, Hazal Yüksel, Alyosha C. Molnar:
A Wideband Highly Integrated and Widely Tunable Transceiver for In-Band Full-Duplex Communication. 1189-1202 - Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx:
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. 1203-1213 - Bodhisatwa Sadhu, Mark A. Ferriss, Alberto Valdes-Garcia:
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance. 1214-1223 - Steven M. Bowers, Amirreza Safaripour, Ali Hajimiri:
Dynamic Polarization Control. 1224-1236 - Brecht François, Patrick Reynaert:
A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS. 1237-1250 - Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. 1251-1262 - Dong-Woo Jee, Dennis Sylvester, David T. Blaauw, Jae-Yoon Sim:
Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform. 1263-1274 - Matthew Loh, Azita Emami-Neyestanak:
Capacitive Proximity Communication With Distributed Alignment Sensing for Origami Biomedical Implants. 1275-1286 - Yi Zhang, Hai Chen, Dongsheng Ma:
A VO-Hopping Reconfigurable RGB LED Driver With Automatic Δ VO Detection and Predictive Peak Current Control. 1287-1298 - Chih-Wei Stanley Yeh, S. Simon Wong:
Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology. 1299-1309 - Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS. 1310-1323 - Ryu Ogiwara, Daisaburo Takashima, Sumiko M. Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga:
Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs. 1324-1331
Volume 50, Number 6, June 2015
- Michael P. Flynn:
New Associate Editor. 1335 - David Murphy, Hooman Darabi, Hao Xu:
A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers. 1336-1350 - Joonsung Bae, Hoi-Jun Yoo:
A 45 µW Injection-Locked FSK Wake-Up Receiver With Frequency-to-Envelope Conversion for Crystal-Less Wireless Body Area Network. 1351-1360 - Jing Zhang, Navneet Sharma, Wooyeol Choi, Dongha Shim, Qian Zhong, Kenneth K. O:
85-to-127 GHz CMOS Signal Generation Using a Quadrature VCO With Passive Coupling and Broadband Harmonic Combining for Rotational Spectroscopy. 1361-1371 - Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. 1372-1381 - Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chiun Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee:
A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching. 1382-1398 - James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa:
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. 1399-1411 - Jiayoon Zhiyu Ru, Claudia Palattella, Paul F. J. Geraedts, Eric A. M. Klumperink, Bram Nauta:
A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging. 1412-1423 - Xiaosen Liu, Edgar Sánchez-Sinencio:
An 86% Efficiency 12 µW Self-Sustaining PV Energy Harvesting System With Hysteresis Regulation and Time-Domain MPPT for IOT Smart Nodes. 1424-1437 - Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon:
An Energy/Illumination-Adaptive CMOS Image Sensor With Reconfigurable Modes of Operations. 1438-1450 - Haifeng Ma, Ronan A. R. van der Zee, Bram Nauta:
A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range. 1451-1462 - Zhidong Liu, Lin Cong, Hoi Lee:
Design of On-Chip Gate Drivers With Power-Efficient High-Speed Level Shifting and Dynamic Timing Control for High-Voltage Synchronous Switching Power Converters. 1463-1477 - Seongjong Kim, Mingoo Seok:
Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique. 1478-1490 - Chun-Hsiung Hung, Meng-Fan Chang, Yih-Shan Yang, Yao-Jen Kuo, Tzu-Neng Lai, Shin-Jang Shen, Jo-Yu Hsu, Shuo-Nan Hung, Hang-Ting Lue, Yen-Hao Shih, Shih-Lin Huang, Ti-Wen Chen, Tzung Shen Chen, Chung Kuang Chen, Chi-Yu Hung, Chih-Yuan Lu:
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations. 1491-1501
Volume 50, Number 7, July 2015
- Michael P. Flynn:
New Associate Editor. 1511 - Angelo Nagari, Kenichi Okada, Marian Verhelst:
Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC). 1512-1515 - Marcello De Matteis, Alessandro Pezzotta, Stefano D'Amico, Andrea Baschirotto:
A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter. 1516-1524 - Wei-Chung Chen, Yi-Ping Su, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Shian-Ru Lin, Tsung-Yen Tsai:
Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology. 1525-1539 - Avishek Biswas, Yildiz Sinangil, Anantha P. Chandrakasan:
A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency. 1540-1549 - Achim Seidel, Marco Salvatore Costa, Joachim Joos, Bernhard Wicht:
Area Efficient Integrated Gate Drivers Based on High-Voltage Charge Storing. 1550-1559 - Athanasios Sarafianos, Michiel Steyaert:
Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter. 1560-1570 - Pyoungwon Park, David Ruffieux, Kofi A. A. Makinwa:
A Thermistor-Based Temperature Sensor for a Real-Time Clock With ± 2 ppm Frequency Stability. 1571-1580 - Sechang Oh, Yoonmyung Lee, Jingcheng Wang, Zhiyoong Foo, Yejoong Kim, Wanyeong Jung, Ziyun Li, David T. Blaauw, Dennis Sylvester:
A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System. 1581-1591 - Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult:
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. 1592-1603 - Paramartha Indirayanti, Tuba Ayhan, Marian Verhelst, Wim Dehaene, Patrick Reynaert:
A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization. 1604-1617 - Matteo Bassi, Junlei Zhao, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto:
A 40-67 GHz Power Amplifier With 13 dBm ℙSAT and 16% PAE in 28 nm CMOS LP. 1618-1628 - Yu Pei, Ying Chen, Domine M. W. Leenaerts, Arthur H. M. van Roermund:
A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications. 1629-1644 - Shiyuan Zheng, Howard C. Luong:
A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA. 1645-1656 - Marco Garampazzi, Paulo M. Mendes, Nicola Codega, Danilo Manstretta, Rinaldo Castello:
Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering. 1657-1668 - Clement Jany, Alexandre Siligaris, Jose-Luis Gonzalez Jimenez, Pierre Vincent, Philippe Ferrari:
A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave Applications. 1669-1679 - Abhirup Lahiri, Nitin Gupta, Anand Kumar, Pradeep Dhadda:
A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process. 1680-1689 - Harald Kröll, Stefan Zwicky, Benjamin Weber, Christoph Roth, David Tschopp, Christian Benkeser, Andreas Peter Burg, Qiuting Huang:
An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity. 1690-1701 - Luca Ravezzi, Hamid Partovi:
Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC. 1702-1710 - Tzu-Chien Hsueh, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper:
An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements. 1711-1721 - Shayan Shahramian, Anthony Chan Carusone:
A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. 1722-1735 - Hyung-Min Lee, Ki Yong Kwon, Wen Li, Bryan Howell, Warren M. Grill, Maysam Ghovanloo:
Corrections to "A Power-Efficient Switched-Capacitor Stimulating System for Electrical/Optical Deep-Brain Stimulation". 1736
Volume 50, Number 8, August 2015
- Andrea Mazzanti, Elad Alon:
Introduction to the Special Issue on the IEEE 2014 Custom Integrated Circuits Conference. 1739-1740 - Jayant Charthad, Marcus J. Weber, Ting Chia Chang, Amin Arbabian:
A mm-Sized Implantable Medical Device (IMD) With Ultrasonic Power Transfer and a Hybrid Bi-Directional Data Link. 1741-1753 - Seokhyeon Jeong, Inhee Lee, David T. Blaauw, Dennis Sylvester:
A 5.8 nW CMOS Wake-Up Timer for Ultra-Low-Power Wireless Applications. 1754-1763 - Martin Kinyua, Ruopeng Wang, Eric G. Soenen:
Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS. 1764-1771 - Bo Wu, Yun Chiu:
A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3. 1772-1784 - Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu:
A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications. 1785-1795 - Chia-Hung Chen, Yi Zhang, Tao He, Patrick Yin Chiang, Gabor C. Temes:
A Micro-Power Two-Step Incremental Analog-to-Digital Converter. 1796-1808 - Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS. 1809-1819 - Aatmesh Shrivastava, Nathan E. Roberts, Osama Ullah Khan, David D. Wentzloff, Benton H. Calhoun:
A 10 mV-Input Boost Converter With Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting With 220 mV Cold-Start and -14.5 dBm, 915 MHz RF Kick-Start. 1820-1832 - Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram:
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. 1833-1847 - Saman Saeedi, Azita Emami-Neyestanak:
An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation. 1848-1860 - Taiyun Chi, Jun Luo, Song Hu, Hua Wang:
A Multi-Phase Sub-Harmonic Injection Locking Technique for Bandwidth Extension in Silicon-Based THz Signal Generation. 1861-1873 - Run Chen, Hossein Hashemi:
Dual-Carrier Aggregation Receiver With Reconfigurable Front-End RF Signal Conditioning. 1874-1888 - Mazhareddin Taghivand, Kamal Aggarwal, Yashar Rajavi, Ada S. Y. Poon:
An Energy Harvesting 2×2 60 GHz Transceiver With Scalable Data Rate of 38-2450 Mb/s for Near-Range Communication. 1889-1902 - Ming-Shuan Chen, Chih-Kong Ken Yang:
A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology. 1903-1916 - Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. 1917-1931 - Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang:
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. 1932-1944 - Keunsoo Song, Sangkwon Lee, Dongkyun Kim, Youngbo Shim, Sangil Park, Bokrim Ko, Duckhwa Hong, Yongsuk Joo, Wooyoung Lee, Yongdeok Cho, Wooyeol Shin, Jaewoong Yun, Hyengouk Lee, Jeonghun Lee, Eunryeong Lee, Namkyu Jang, Jaemo Yang, Haekang Jung, Joohwan Cho, Hyeongon Kim, Jinkook Kim:
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques. 1945-1959
Volume 50, Number 9, September 2015
- Leonardo Vera, John R. Long:
A DC-100 GHz Active Frequency Doubler With a Low-Voltage Multiplier Core. 1963-1973 - Ercan Kaymaksut, Patrick Reynaert:
Dual-Mode CMOS Doherty LTE Power Amplifier With Symmetric Hybrid Transformer. 1974-1987 - Yaohua Zhao, Pui-In Mak, Rui Paulo Martins, Franco Maloberti:
A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad. 1988-2001 - Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx:
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. 2002-2011 - Abhishek Ghosh, Sudhakar Pamarti:
Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC. 2012-2024 - Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq:
A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS. 2025-2036 - Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
A Reference-Less Single-Loop Half-Rate Binary CDR. 2037-2047 - Sui Huang, Jun Cao, Michael M. Green:
An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS. 2048-2060 - Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng:
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies. 2061-2073 - Davide De Caro, Fabio Tessitore, Gianfranco Vai, Nicola Imperato, Nicola Petra, Ettore Napoli, Claudio Parrella, Antonio G. M. Strollo:
A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS. 2074-2089 - Jiawei Xu, Benjamin Busze, Chris Van Hoof, Kofi A. A. Makinwa, Refet Firat Yazicioglu:
A 15-Channel Digital Active Electrode System for Multi-Parameter Biopotential Measurement. 2090-2100 - Honglin Xu, Xiaowei Liu, Liang Yin:
A Closed-Loop ΣΔ Interface for a High-Q Micromechanical Capacitive Accelerometer With 200 ng/√Hz Input Noise Density. 2101-2112 - Yang Zhao, Jian Zhao, Xi Wang, Guo Ming Xia, An Ping Qiu, Yan Su, Yong Ping Xu:
A Sub-µg Bias-Instability MEMS Oscillating Accelerometer With an Ultra-Low-Noise Read-Out Circuit in CMOS. 2113-2126 - Xiao Pu, Mikel Ash, Krishnaswamy Nagaraj, Joonsung Park, Steve Vu, Paul Kimelman, Sean de la Haye:
An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4°C (3σ) From - 40°C to 130°C. 2127-2137 - Andrew Berkovich, Michela Lecca, Leonardo Gasparini, Pamela Abshire, Massimo Gottardi:
A 30 µW 30 fps 110 × 110 Pixels Vision Sensor Embedding Local Binary Patterns. 2138-2148 - Minhao Yang, Shih-Chii Liu, Tobi Delbrück:
A Dynamic Vision Sensor With 1% Temporal Contrast Sensitivity and In-Pixel Asynchronous Delta Modulator for Event Encoding. 2149-2160 - Chih-Wei Chen, Ayman A. Fayed:
A Low-Power Dual-Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS. 2161-2173 - Zhidong Liu, Hoi Lee:
A 26 W 97%-Efficiency Fast-Settling Dimmable LED Driver With Dual-nMOS-Sensing Based Glitch-Tolerant Synchronous Current Control for High-Brightness Solid-State Lighting Applications. 2174-2187 - Meng-Fan Chang, Yu-Fan Lin, Yen-Chen Liu, Jui-Jen Wu, Shin-Jang Shen, Wu-Chin Tsai, Yu-Der Chih:
An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros. 2188-2198 - Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register. 2199-2211 - Yu-Jung Chen, Chao-Hsien Hsu, Chung-Yao Hung, Chia-Ming Chang, Shan-Yi Chuang, Liang-Gee Chen, Shao-Yi Chien:
A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques. 2212-2223 - Christian Venerus, Ian Galton:
Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO". 2224
Volume 50, Number 10, October 2015
- Waleed Khalil:
Introduction to the Special Section on the 2014 Compound Semiconductor Integrated Circuit Symposium. 2227 - Paolo Valerio Testa, Guido Belfiore, Robert Paulo, Corrado Carta, Frank Ellinger:
170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier. 2228-2238 - Alexander Tomkins, Alan Poon, Eric Juntunen, Ahmed El-Gabaly, Grigori Temkine, Yat-Loong To, Craig Farnsworth, Arash Tabibiazar, Mohammad Fakharzadeh, Saman Jafarlou, Ahmed Abdellatif, Hatem Tawfik, Brad Lynch, Mihai Tazlauanu, Ronald Glibbery:
A 60 GHz, 802.11ad/WiGig-Compliant Transceiver for Infrastructure and Mobile Applications in 130 nm SiGe BiCMOS. 2239-2255 - Shinwon Kang, Siva V. Thyagarajan, Ali M. Niknejad:
A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS. 2256-2267 - Siva V. Thyagarajan, Shinwon Kang, Ali M. Niknejad:
A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOS. 2268-2280 - Dongju Lee, Minjae Lee:
Low Flicker Noise, Odd-Phase Master LO Active Mixer Using a Low Switching Frequency Scheme. 2281-2293 - In-Young Lee, Donggu Im, Jinho Ko, Sang-Gug Lee:
A 50-450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP3, +12 dBm P1 dB, and 15 dB Noise Figure. 2294-2305 - Ameya Bhide, Atila Alvandpour:
An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS. 2306-2318 - Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung, Seung-Tak Ryu:
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. 2319-2330 - Yong Lim, Michael P. Flynn:
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers. 2331-2341 - Younghyun Yoon, Danbi Choi, Jeongjin Roh:
A 0.4 V 63 µW 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator. 2342-2352 - Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo Martins, Franco Maloberti:
Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate. 2353-2366 - Minseob Shim, Jungmoon Kim, Junwon Jeong, Sejin Park, Chulwoo Kim:
Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking Time. 2367-2379 - Sung-Wan Hong, Sang-Hui Park, Tae-Hwang Kong, Gyu-Hyeong Cho:
Inverting Buck-Boost DC-DC Converter for Mobile AMOLED Display Using Real-Time Self-Tuned Minimum Power-Loss Tracking (MPLT) Scheme With Lossless Soft-Switching for Discontinuous Conduction Mode. 2380-2393 - Josep Maria Margarit, German Vergara, Victor Villamayor, Raul Gutierrez-Alvarez, Carlos Fernández-Montojo, Lluís Terés, Francisco Serra-Graells:
A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications. 2394-2405 - Juan Mata Pavia, Mario Scandini, Scott Lindner, Martin Wolf, Edoardo Charbon:
A 1 × 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography. 2406-2418 - Numa Couniot, Guerric de Streel, François Botman, Angelo Kuti Lusala, Denis Flandre, David Bol:
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. 2419-2430 - Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Junho Cheon, Seung-Tak Ryu:
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. 2431-2440 - Byung-Do Yang:
Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme. 2441-2450 - Woong Choi, Gyuseong Kang, Jongsun Park:
A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder. 2451-2462 - Shayan Shahramian, Anthony Chan Carusone:
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS". 2463 - P. V. Ananda Mohan, Yaohua Zhao, Pui-In Mak, Rui Paulo Martins, Franco Maloberti:
Corrections to "A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad". 2464
Volume 50, Number 11, November 2015
- Michael P. Flynn:
New Associate Editor. 2471 - Stefan Rusu, Gregory Chen:
Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). 2472-2474 - Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. 2475-2490 - Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin:
A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C2. 2491-2500 - Sunjoo Hong, Jaehyuk Lee, Joonsung Bae, Hoi-Jun Yoo:
A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lung Ventilation Monitoring System. 2501-2512 - Injoon Hong, Gyeonghoon Kim, Youchang Kim, Donghyun Kim, Byeong-Gyu Nam, Hoi-Jun Yoo:
A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor. 2513-2523 - Shih-Hsiung Chien, Ting-Hsuan Hung, Szu-Yu Huang, Tai-Haur Kuo:
A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter With Transient-Optimized Feedback Circuit. 2524-2532 - Jen-Huan Tsai, Sheng-An Ko, Chia-Wei Wang, Yang-Chi Yen, Hui-Huan Wang, Po-Chiun Huang, Po-Hsiang Lan, Meng-Hung Shen:
A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics. 2533-2548 - Hyunwoo Cho, Hyungwoo Lee, Joonsung Bae, Hoi-Jun Yoo:
A 5.2 mW IEEE 802.15.6 HBC Standard Compatible Transceiver With Power Efficient Delay-Locked-Loop Based BPSK Demodulator. 2549-2559 - Dixian Zhao, Patrick Reynaert:
A 40 nm CMOS E-Band Transmitter With Compact and Symmetrical Layout Floor-Plans. 2560-2571 - Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, Zongming Jin, Xiliang Liu, Zhihua Wang, Yichuang Sun, Baoyong Chi:
A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS. 2572-2590 - Harish Kundur Subramaniyan, Eric A. M. Klumperink, Venkatesh Srinivasan, Ali Kiaei, Bram Nauta:
RF Transconductor Linearization Robust to Process, Voltage and Temperature Variations. 2591-2602 - Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. 2603-2612 - Hyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, Inhwa Jung, Seongjin Kang, Ohkyu Kwon, Koeun Cheon, Donghwan Seol, Jong-Ho Kang, Gunwoo Park, Yunsaing Kim:
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel. 2613-2624 - Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen:
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery. 2625-2634 - Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang:
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. 2635-2644 - Chun-Cheng Liu, Che-Hsun Kuo, Ying-Zu Lin:
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS. 2645-2654 - Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu:
A 0.022 mm2 98.5 dB SNDR Hybrid Audio ΔΣ Modulator With Digital ELD Compensation in 28 nm CMOS. 2655-2664 - Yu-Hsien Kao, Ta-Shun Chu:
A Direct-Sampling Pulsed Time-of-Flight Radar With Frequency-Defined Vernier Digital-to-Time Converter in 65 nm CMOS. 2665-2677 - Salvatore Levantino, Giovanni Marucci, Giovanni Marzin, Andrea Fenaroli, Carlo Samori, Andrea L. Lacaita:
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop. 2678-2691 - Kristian N. Madsen, Timothy D. Gathman, Saeid Daneshgar, Thomas C. Oh, James Chingwei Li, James F. Buckwalter:
A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process. 2692-2702 - Ryan Clarke, Mitchell R. LeRoy, Srikumar Raman, Tuhin Guha Neogi, Russell P. Kraft, John F. McDonald:
140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology. 2703-2713 - Hansraj Bhamra, Young-Joon Kim, Jithin Joseph, John Lynch, Oren Z. Gall, Henry Mei, Chuizhou Meng, Jui-Wei Tsai, Pedro P. Irazoqui:
A 24µW, Batteryless, Crystal-free, Multinode Synchronized SoC "Bionode" for Wireless Prosthesis Control. 2714-2727 - Muhammad Awais Bin Altaf, Chen Zhang, Jerald Yoo:
A 16-Channel Patient-Specific Seizure Onset and Termination Detection SoC With Impedance-Adaptive Transcranial Electrical Stimulator. 2728-2740 - Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata:
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. 2741-2749 - Kai Ho Mak, Ming Wai Lau, Jianping Guo, Tin Wai Mui, Marco Ho, Wang Ling Goh, Ka Nang Leung:
A 0.7V 24µA Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW. 2750-2757 - Guolei Yu, Kin Wai Roy Chew, Zhuochao Sun, Howard Tang, Liter Siek:
A 400 nW Single-Inductor Dual-Input-Tri-Output DC-DC Buck-Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting. 2758-2772 - Teng Yang, Seongjong Kim, Peter R. Kinget, Mingoo Seok:
Compact and Supply-Voltage-Scalable Temperature Sensors for Dense On-Chip Thermal Monitoring. 2773-2785 - Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chrong Jung Lin, Ku-Feng Lin, Yu-Der Chih, Tsung-Yung Jonathan Chang:
Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations. 2786-2795
Volume 50, Number 12, December 2015
- Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynänen, Kenichi Okada, Jaeha Kim:
Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. 2799-2803 - Yoshinori Kusuda:
A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks and Input Bias Current Trimming. 2804-2813 - Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator. 2814-2824 - Min-Yong Jung, Sang-Hui Park, Jun-Suk Bang, Gyu-Hyeong Cho:
An Error-Based Controlled Single-Inductor 10-Output DC-DC Buck Converter With High Efficiency Under Light Load Using Adaptive Pulse Modulation. 2825-2838 - Mehdi Kiani, Byunghun Lee, Pyungwoo Yeon, Maysam Ghovanloo:
A Q-Modulation Technique for Efficient Inductive Power Transmission. 2839-2848 - Hans Meyvaert, Gerard Villar Pique, Ravi Karadi, Henk Jan Bergveld, Michiel S. J. Steyaert:
A Light-Load-Efficient 11/1 Switched-Capacitor DC-DC Converter With 94.7% Efficiency While Delivering 100 mW at 3.3 V. 2849-2860 - Christopher Schaef, Jason T. Stauth:
A 3-Phase Resonant Switched Capacitor Converter Delivering 7.7 W at 85% Efficiency Using 1.1 nH PCB Trace Inductors. 2861-2869 - Chen-Yen Ho, Cong Liu, Chi-Lun Lo, Hung-Chieh Tsai, Tze-Chien Wang, Yu-Hsin Lin:
A 4.5 mW CT Self-Coupled ΔΣ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation. 2870-2879 - Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee:
A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS. 2880-2890 - Martin Kramer, Erwin Janssen, Kostas Doris, Boris Murmann:
A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS. 2891-2900 - Yong Lim, Michael P. Flynn:
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC. 2901-2911 - Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee:
A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers. 2912-2921 - Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Bryan Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Yuan Yao, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen:
A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS. 2922-2934 - Ruonan Han, Chen Jiang, Ali Mostajeran, Mohammad Emadi, Hamidreza Aghasi, Hani Sherry, Andreia Cathelin, Ehsan Afshari:
A SiGe Terahertz Heterodyne Imaging Transmitter With 3.3 mW Radiated Power and Fully-Integrated Phase-Locked Loop. 2935-2947 - Hao Wu, Mohyee Mikhemar, David Murphy, Hooman Darabi, Mau-Chung Frank Chang:
A Blocker-Tolerant Inductor-Less Wideband Receiver With Phase and Thermal Noise Cancellation. 2948-2964 - Anith Selvakumar, Meysam Zargham, Antonio Liscidini:
Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications. 2965-2974 - Atsushi Shirane, Yiming Fang, Haowei Tan, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter. 2975-2987 - Colin Weltin-Wu, Guobi Zhao, Ian Galton:
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion. 2988-3002 - Dirk-Jan van den Broek, Eric A. M. Klumperink, Bram Nauta:
An In-Band Full-Duplex Radio Receiver With a Passive Vector Modulator Downmixer for Self-Interference Cancellation. 3003-3014 - Jin Zhou, Tsung-Hao Chuang, Tolga Dinc, Harish Krishnaswamy:
Integrated Wideband Self-Interference Cancellation in the RF Domain for FDD and Full-Duplex Wireless. 3015-3031 - Run Chen, Hossein Hashemi:
Reconfigurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation. 3032-3046 - Rabia Tugce Yazicigil, Tanbir Haque, Michael R. Whalen, Jeffrey Yuan, John Wright, Peter R. Kinget:
Wideband Rapid Interferer Detector Exploiting Compressed Sampling With a Quadrature Analog-to-Information Converter. 3047-3064 - Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. 3065-3076 - Jan Prummel, Michail Papamichail, John Willms, Rahul Todi, William Aartsen, Wim Kruiskamp, Johan Haanstra, Enno Opbroek, Soren Rievers, Peter Seesink, Jan van Gorsel, Harrie Woering, Chris Smit:
A 10 mW Bluetooth Low-Energy Transceiver With On-Chip Matching. 3077-3088 - Bo Zhang, Karapet Khanoyan, Hamid Hatamkhani, Haitao Tong, Kangmin Hu, Siavash Fallahi, Mohammed M. Abdul-Latif, Kambiz Vakilian, Ichiro Fujimori, Anthony Brewster:
A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS. 3089-3100 - Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu:
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. 3101-3119 - Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli:
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. 3120-3132 - Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. 3133-3144 - Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang:
A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS. 3145-3159 - Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu:
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. 3160-3174
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