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ORCIDKiyoharu Hamaguchi
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2020 – today
- 2023
[j17]Kiyoharu Hamaguchi:
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage. IPSJ Trans. Syst. LSI Des. Methodol. 16: 45-53 (2023)
2010 – 2019
- 2019
- [j16]Kiyoharu Hamaguchi:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 866 (2019) - 2018
- [j15]Kiyoharu Hamaguchi:
Applying an SMT Solver to Coverage-Driven Design Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1053-1056 (2018) - [j14]Kiyoharu Hamaguchi:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2221 (2018) - [c17]Mami Miyamoto, Kiyoharu Hamaguchi:
Extracting hardware assertions including word-level relations over multiple clock cycles. ISQED 2018: 244-250 - 2017
- [j13]Yosuke Kakiuchi, Kiyoharu Hamaguchi:
Coverage-Driven Design Verification Using a Diverse SAT Solver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1481-1487 (2017) - 2011
- [j12]Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi:
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts. Inf. Media Technol. 6(4): 1116-1127 (2011) - [j11]Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi:
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts. IPSJ Trans. Syst. LSI Des. Methodol. 4: 210-221 (2011) - 2010
- [j10]Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara:
Approximate Model Checking Using a Subset of First-order Logic. Inf. Media Technol. 5(4): 1132-1146 (2010) - [j9]Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3: 105-117 (2010) - [j8]Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara:
Approximate Model Checking Using a Subset of First-order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3: 268-282 (2010)
2000 – 2009
- 2009
- [j7]Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Checker Generation of Assertions with Local Variables for Model Checking. Inf. Media Technol. 4(2): 227-239 (2009) - [j6]Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Checker Generation of Assertions with Local Variables for Model Checking. IPSJ Trans. Syst. LSI Des. Methodol. 2: 80-92 (2009) - 2008
- [c16]Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. ATVA 2008: 318-331 - 2007
- [j5]Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2778-2789 (2007) - 2006
- [j4]Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition. IEICE Trans. Inf. Syst. 89-D(3): 1120-1127 (2006) - 2005
- [c15]Yosuke Kakiuchi, A. Kitajima, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Automatic monitor generation from regular expression based specifications for module interface verification. ISCAS (4) 2005: 3555-3558 - 2004
- [j3]Kiyoharu Hamaguchi:
Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions. IEICE Trans. Inf. Syst. 87-D(3): 637-641 (2004) - [c14]Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas. ATVA 2004: 108-119 - 2001
- [c13]Kiyoharu Hamaguchi:
Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions. HLDVT 2001: 25-30 - 2000
- [c12]Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction. COCOON 2000: 467-476 - [c11]Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara:
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. FMCAD 2000: 455-469
1990 – 1999
- 1997
- [j2]Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi:
Another Look at LTL Model Checking. Formal Methods Syst. Des. 10(1): 47-71 (1997) - 1995
- [c10]Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima:
Efficient construction of binary moment diagrams for verifying arithmetic circuits. ICCAD 1995: 78-82 - 1994
- [c9]Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi:
Another Look at LTL Model Checking. CAV 1994: 415-427 - 1993
- [c8]Seiichiro Tani, Kiyoharu Hamaguchi, Shuzo Yajima:
The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams. ISAAC 1993: 389-398 - 1992
- [j1]Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima:
Infinity-Regular Temporal Logic and its Model Checking Problem. Theor. Comput. Sci. 103(2): 191-204 (1992) - [c7]Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima:
Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic. CAV 1992: 206-219 - 1991
- [c6]Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima:
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. CAV 1991: 214-224 - [c5]Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima:
Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic. CAV 1991: 410-420 - 1990
- [c4]Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi:
Vectorized Model Checking for Computation Tree Logic. CAV 1990: 44-53 - [c3]Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima:
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity. CAV 1990: 253-262 - [c2]Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi:
Vectorized Model Checking for Computation Tree Logic. CAV (DIMACS/AMS volume) 1990: 219-230 - [c1]Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima:
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity. CAV (DIMACS/AMS volume) 1990: 551-564
Coauthor Index
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