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2020 – today
- 2024
[j36]Yu-Chuan Yen
, Meng-Jing Li, Yi-Ting Li, Yung-Chih Chen, Ihao Chen, Chun-Yao Wang:
9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4676-4686 (2024)- [c74]Pei-Pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, Chun-Yao Wang:
LOOPLock 3.0: A Robust Cyclic Logic Locking Approach. ASPDAC 2024: 594-599 - [c73]Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang:
A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE 2024: 1-2 - [c72]Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, Chun-Yao Wang:
IR drop Prediction Based on Machine Learning and Pattern Reduction. ACM Great Lakes Symposium on VLSI 2024: 516-519 - [c71]Wuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang:
Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method. SOCC 2024: 1-6 - 2023
- [j35]Yung-Chih Chen, Li-Cheng Zheng, Hao-Ju Chang:
Don't-Care-Based Logic Optimization for Threshold Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2980-2993 (2023) - [j34]Meng-Jing Li, Yu-Chuan Yen, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Constructive Approach for Threshold Function Identification. ACM Trans. Design Autom. Electr. Syst. 28(5): 86:1-86:19 (2023) - [c70]Chun-Ting Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee. ASP-DAC 2023: 146-151 - [c69]Yung-Chih Chen, Feng-Jie Chao:
Optimization of Reversible Logic Networks with Gate Sharing. ASP-DAC 2023: 166-171 - [c68]Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli. ASP-DAC 2023: 696-701 - [c67]RuiJie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang:
Expanding In-Cone Obfuscated Tree for Anti SAT Attack. DATE 2023: 1-6 - [c66]Ting-Yu Yeh, Yueh Cho, Yung-Chih Chen:
An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification. DATE 2023: 1-6 - [c65]Hsin-Ping Yen, Shiuan-Hau Huang, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation. ISQED 2023: 1-8 - 2022
- [j33]Xiang-Min Yang, Pei-Pei Chen, Hsiao-Yu Chiang, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 29-34 (2022) - [j32]Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Majority Logic Circuit Minimization Using Node Addition and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 642-655 (2022) - [j31]Chia-Chun Lin, Ciao-Syun Lin, You-Hsuen Tsai, Yung-Chih Chen, Chun-Yao Wang:
Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1412-1422 (2022) - [j30]Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4821-4825 (2022) - [j29]Hsu-Chi Lee, Yun-Chih Lu, Yu-Chen Lin, Wei-Lin Lai, Hsiang-Yuan Hsieh, Boy-Yiing Jaw, Chin-Tang Chuang, Yung-Chih Chen, Yi-Jan Emery Chen:
A High Voltage Driving Chiplet in Standard 0.18-μm CMOS for Micro-Pixelated LED Displays Integrated With LTPS TFTs. IEEE Trans. Circuits Syst. Video Technol. 32(10): 7204-7211 (2022) - [c64]Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0. ICCAD 2022: 155:1-155:7 - 2021
- [j28]Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, Chun-Yao Wang:
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. ACM J. Emerg. Technol. Comput. Syst. 17(2): 15:1-15:23 (2021) - [j27]Yi-Wen Hung, Yung-Chih Chen, Chi Lo, Austin Go So, Shih-Chieh Chang:
Dynamic Workload Allocation for Edge Computing. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 519-529 (2021) - [c63]Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, Chun-Yao Wang:
A General Equivalence Checking Framework for Multivalued Logic. ASP-DAC 2021: 61-66 - [c62]Kit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
An Efficient Approximate Node Merging with an Error Rate Guarantee. ASP-DAC 2021: 266-271 - [c61]Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou:
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. ASP-DAC 2021: 469-474 - [c60]Yung-Chih Chen, Jun-Wei Hsieh, Yao-Hong Yang, Chien-Hung Lee, Pei-Yi Yu, Ping-Yang Chen, Arpita Samanta Santa:
Towards Deep Learning-Based Sarcopenia Screening with Body Joint Composition Analysis. ICIP 2021: 3807-3811 - [c59]Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays. ISQED 2021: 316 - [c58]Wen-Chih Hsu, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
On Reduction of Computations for Threshold Function Identification. SoCC 2021: 146-151 - [c57]Yi-Ting Lin, Chun-Jui Chen, Pei-Yi Kuo, Si-Huei Lee, Chia-Chun Lin, Yun-Ju Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
An IMU-aided Fitness System. SoCC 2021: 224-229 - [c56]Shiuan-Hau Huang, Hsin-Ping Yen, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
Cluster Tool Performance Analysis using Graph Database. SoCC 2021: 230-235 - 2020
- [j26]Chi-Jim Chen, Tun-Wen Pai, Hui-Huang Hsu, Chien-Hung Lee, Kuo-Su Chen, Yung-Chih Chen:
Prediction of chronic kidney disease stages by renal ultrasound imaging. Enterp. Inf. Syst. 14(2): 178-195 (2020) - [j25]Yung-Chih Chen:
SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(5): 733-740 (2020) - [j24]Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, Chun-Yao Wang:
LOOPLock: Logic Optimization-Based Cyclic Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2178-2191 (2020) - [j23]Chia-Chun Lin, Chin-Heng Liu, Yung-Chih Chen, Chun-Yao Wang:
A New Necessary Condition for Threshold Function Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5304-5308 (2020) - [c55]Yung-Chih Chen, Hao-Ju Chang, Li-Cheng Zheng:
Don't-Care-Based Node Minimization for Threshold Logic Networks. DAC 2020: 1-6 - [c54]Xiang-Xiu Wu, Yi-Wen Hung, Yung-Chih Chen, Shih-Chieh Chang:
Accuracy Tolerant Neural Networks Under Aggressive Power Optimization. DATE 2020: 774-779 - [c53]Ya-Chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen, Chun-Yao Wang:
A Convolutional Result Sharing Approach for Binarized Neural Network Inference. DATE 2020: 780-785 - [c52]Teng-Chia Wang, Yan-Ping Chang, Chun-Jui Chen, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement. ISQED 2020: 173-178 - [c51]Chun-Jui Chen, Yi-Ting Lin, Chia-Chun Lin, Yung-Chih Chen, Yun-Ju Lee, Chun-Yao Wang:
Rehabilitation System for Limbs using IMUs. ISQED 2020: 285-291 - [c50]Chia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen, Chun-Yao Wang:
A Dynamic Expansion Order Algorithm for the SAT-based Minimization. SoCC 2020: 271-276
2010 – 2019
- 2019
- [j22]Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita:
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2284-2297 (2019) - [j21]Yung-Chih Chen, Li-Cheng Zheng, Fu-Lian Wong:
Optimization of Threshold Logic Networks with Node Merging and Wire Replacement. ACM Trans. Design Autom. Electr. Syst. 24(6): 67:1-67:18 (2019) - [c49]De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
A Glitch Key-Gate for Logic Locking. SoCC 2019: 74-79 - [c48]Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises. SoCC 2019: 197-202 - 2018
- [j20]Yung-Chih Chen:
Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption. ACM Trans. Design Autom. Electr. Syst. 23(4): 52:1-52:25 (2018) - [j19]Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee, Shih-Chieh Chang:
Contactless Testing for Prebond Interposers. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1005-1014 (2018) - [j18]Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2842-2852 (2018) - [c47]Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Logic optimization with considering boolean relations. DATE 2018: 761-766 - [c46]Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. DATE 2018: 773-778 - [c45]Chia-Cheng Wu, Tung-Yuan Lee, Yung-An Lai, Hsin-Pei Wang, De-Xuan Ji, Yan-Ping Chang, Teng-Chia Wang, Chin-Heng Liu, Chun-Yao Wang, Yung-Chih Chen:
A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification. ACM Great Lakes Symposium on VLSI 2018: 447-450 - [c44]Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang:
Using range-equivalent circuits for facilitating bounded sequential equivalence checking. VLSI-DAT 2018: 1-4 - [c43]Fu-Lian Wong, Li-Cheng Zheng, Yung-Chih Chen:
Optimization of threshold logic networks with ODC-based node merging. VLSI-DAT 2018: 1-4 - 2017
- [j17]Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan:
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1477-1489 (2017) - [c42]Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu:
Majority logic circuits optimisation by node merging. ASP-DAC 2017: 714-719 - [c41]Yung-Chih Chen:
Tree-Based Logic Encryption for Resisting SAT Attack. ATS 2017: 46-51 - [c40]Chia-Chun Lin, Chiao-Wei Huang, Chun-Yao Wang, Yung-Chih Chen:
In&Out: Restructuring for threshold logic network optimization. ISQED 2017: 413-418 - 2016
- [j16]Yung-Chih Chen, Don Towsley, Ramin Khalili:
MSPlayer: Multi-Source and Multi-Path Video Streaming. IEEE J. Sel. Areas Commun. 34(8): 2198-2206 (2016) - [j15]Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm. J. Multiple Valued Log. Soft Comput. 27(1): 1-19 (2016) - [j14]Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Chiou-Ting Hsu:
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks. IEEE Trans. Multi Scale Comput. Syst. 2(4): 225-233 (2016) - [j13]Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan:
Area-Aware Decomposition for Single-Electron Transistor Arrays. ACM Trans. Design Autom. Electr. Syst. 21(4): 70:1-70:20 (2016) - [j12]Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2321-2334 (2016) - [c39]Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
MajorSat: A SAT solver to majority logic. ASP-DAC 2016: 480-485 - [c38]Yung-Chih Chen, Runyi Wang, Yan-Ping Chang:
Fast synthesis of threshold logic networks with optimization. ASP-DAC 2016: 486-491 - 2015
- [j11]Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen:
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 615-628 (2015) - [j10]Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan:
Synthesis for Width Minimization in the Single-Electron Transistor Array. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2862-2875 (2015) - [c37]Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. ASP-DAC 2015: 118-123 - [c36]Yeon-Sup Lim, Yung-Chih Chen, Erich M. Nahum, Don Towsley, Richard J. Gibbens, Emmanuel Cecchet:
Design, implementation, and evaluation of energy-aware multi-path TCP. CoNEXT 2015: 30:1-30:13 - [c35]Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang:
Using structural relations for checking combinationality of cyclic circuits. DATE 2015: 325-328 - [c34]Yung-Chih Chen, H. J. Lee, K. H. Lin:
Measurement of body joint angles for physical therapy based on mean shift tracking using two low cost Kinect images. EMBC 2015: 703-706 - [c33]Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang:
Synthesis and verification of cyclic combinational circuits. SoCC 2015: 257-262 - 2014
- [j9]Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu:
Hybrid LUT and SOP Reconfigurable Architecture. J. Inf. Sci. Eng. 30(1): 65-84 (2014) - [c32]Yung-Chih Chen, Don Towsley, Ramin Khalili:
MSPlayer: Multi-Source and multi-Path LeverAged YoutubER. CoNEXT 2014: 263-270 - [c31]Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang:
Rewiring for threshold logic circuit minimization. DATE 2014: 1-6 - [c30]Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
Width minimization in the Single-Electron Transistor array synthesis. DATE 2014: 1-4 - [c29]Chi-Jim Chen, Tun-Wen Pai, Hamido Fujita, Chien-Hung Lee, Yang-Ting Chen, Kuo-Su Chen, Yung-Chih Chen:
Stage diagnosis for Chronic Kidney Disease based on ultrasonography. FSKD 2014: 525-530 - [c28]Yeon-Sup Lim, Yung-Chih Chen, Erich M. Nahum, Don Towsley, Kang-Won Lee:
Cross-layer path management in multi-path transport protocol for mobile devices. INFOCOM 2014: 1815-1823 - [c27]Yung-Chih Chen, Don Towsley:
On bufferbloat and delay analysis of multipath TCP in wireless networks. Networking 2014: 1-9 - [c26]Yeon-Sup Lim, Yung-Chih Chen, Erich M. Nahum, Don Towsley, Richard J. Gibbens:
How green is multipath TCP for mobile devices? AllThingsCellular@SIGCOMM 2014: 3-8 - [c25]Juhoon Kim, Yung-Chih Chen, Ramin Khalili, Don Towsley, Anja Feldmann:
Multi-source multipath HTTP (mHTTP): a proposal. SIGMETRICS 2014: 583-584 - [c24]Yung-Chih Chen, Kung-Ming Ji:
SAT-based complete logic implication with application to logic optimization. VLSI-DAT 2014: 1-4 - [i3]Yeon-Sup Lim, Yung-Chih Chen, Erich M. Nahum, Don Towsley, Richard J. Gibbens:
Improving Energy Efficiency of MPTCP for Mobile Devices. CoRR abs/1406.4463 (2014) - [i2]Yung-Chih Chen, Don Towsley, Ramin Khalili:
MSPlayer: Multi-Source and multi-Path LeverAged YoutubER. CoRR abs/1406.6772 (2014) - 2013
- [j8]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. ACM J. Emerg. Technol. Comput. Syst. 9(1): 5:1-5:20 (2013) - [j7]Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1473-1483 (2013) - [c23]Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
On reconfigurable single-electron transistor arrays synthesis using reordering techniques. DATE 2013: 1807-1812 - [c22]Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
Sensitization criterion for threshold logic circuits and its application. ICCAD 2013: 226-233 - [c21]Yung-Chih Chen, Yeon-Sup Lim, Richard J. Gibbens, Erich M. Nahum, Ramin Khalili, Don Towsley:
A measurement-based study of MultiPath TCP performance over wireless networks. Internet Measurement Conference 2013: 455-468 - [c20]Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
Pattern generation for Mutation Analysis using Genetic Algorithms. ISCAS 2013: 2545-2548 - [i1]Juhoon Kim, Ramin Khalili, Anja Feldmann, Yung-Chih Chen, Don Towsley:
Multi-Source Multi-Path HTTP (mHTTP): A Proposal. CoRR abs/1310.2748 (2013) - 2012
- [j6]Yung-Chih Chen, Chun-Yao Wang:
Logic Restructuring Using Node Addition and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 260-270 (2012) - [c19]Chih-Yin Ho, Tun-Wen Pai, Yuan-Chi Peng, Chien-Hung Lee, Yung-Chih Chen, Yang-Ting Chen, Kuo-Su Chen:
Ultrasonography Image Analysis for Detection and Classification of Chronic Kidney Disease. CISIS 2012: 624-629 - [c18]Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen:
A probabilistic analysis method for functional qualification under Mutation Analysis. DATE 2012: 147-152 - [c17]Yung-Chih Chen, Jim Kurose, Don Towsley:
A mixed queueing network model of mobility in a campus wireless network. INFOCOM 2012: 2656-2660 - 2011
- [c16]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
Automated mapping for reconfigurable single-electron transistor arrays. DAC 2011: 878-883 - [c15]Chen-Sen Ouyang, Chih-Chung Wang, Yung-Chih Chen:
A recursive SVD-based self-constructing rule generation for neuro-fuzzy system modeling. ICMLC 2011: 172-177 - [c14]Yung-Chih Chen, Jim Kurose, Don Towsley:
A simple queueing network model of mobility in a campus wireless network. S3@MobiCom 2011: 5-8 - 2010
- [j5]Ling-Jyh Chen, Yung-Chih Chen:
An Analytical Study of People Mobility in Opportunistic Networks. J. Inf. Sci. Eng. 26(1): 197-214 (2010) - [j4]Yung-Chih Chen, Chun-Yao Wang:
Fast Node Merging With Don't Cares Using Logic Implications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1827-1832 (2010) - [c13]Yung-Chih Chen, Chun-Yao Wang:
Node addition and removal in the presence of don't cares. DAC 2010: 505-510 - [c12]Yung-Chih Chen, Elisha J. Rosensweig, Jim Kurose, Donald F. Towsley:
Group detection in mobility traces. IWCMC 2010: 875-879
2000 – 2009
- 2009
- [j3]Chen-Hsuan Lin, Chun-Yao Wang, Yung-Chih Chen:
Dependent-Latch Identification in Reachable State Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1113-1126 (2009) - [c11]Yung-Chih Chen, Chun-Yao Wang:
Enhancing SAT-based sequential depth computation by pruning search space. ACM Great Lakes Symposium on VLSI 2009: 397-400 - [c10]Yung-Chih Chen, Chun-Yao Wang:
Fast detection of node mergers using logic implications. ICCAD 2009: 785-788 - [c9]Meng-Syue Chan, Chun-Yao Wang, Yung-Chih Chen:
An efficient approach to sip design integration. ISQED 2009: 241-247 - [c8]Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang:
A novel ACO-based pattern generation for peak power estimation in VLSI circuits. ISQED 2009: 317-323 - 2008
- [j2]Yung-Chih Chen, Chun-Yao Wang:
An Implicit Approach to Minimizing Range-Equivalent Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1942-1955 (2008) - [j1]Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen:
Novel Probabilistic Combinational Equivalence Checking. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 365-375 (2008) - [c7]Xiaofeng Lu, Yung-Chih Chen, Ian X. Y. Leung, Zhang Xiong, Pietro Liò:
A Novel Mobility Model from a Heterogeneous Military MANET Trace. ADHOC-NOW 2008: 463-474 - [c6]Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen:
A Statistic-Based Approach to Testability Analysis. ISQED 2008: 267-270 - 2007
- [c5]Ling-Jyh Chen, Yung-Chih Chen, Tony Sun, Paruvelli Sreedevi, Kuan-Ta Chen, Chen-Hung Yu, Hao-Hua Chu:
Finding Self-Similarities in Opportunistic People Networks. INFOCOM 2007: 2286-2290 - 2006
- [c4]Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen:
Language-Based High Level Transaction Extraction on On-chip Buses. ISQED 2006: 231-236 - [c3]Ling-Jyh Chen, Tony Sun, Yung-Chih Chen:
Improving Bluetooth EDR Data Throughput Using FEC and Interleaving. MSN 2006: 724-735 - [c2]Ling-Jyh Chen, Chen-Hung Yu, Tony Sun, Yung-Chih Chen, Hao-Hua Chu:
A hybrid routing approach for opportunistic networks. CHANTS@SIGCOMM 2006: 213-220 - 2005
- [c1]Yung-Chih Chen, Chun-Yao Wang:
An Improved Approach for AlternativeWires Identi.cation. ICCD 2005: 711-716
Coauthor Index
Don Towsley
aka: Donald F. Towsley
aka: Donald F. Towsley
Narayanan Vijaykrishnan
aka: Vijaykrishnan Narayanan
aka: Vijaykrishnan Narayanan
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