research-article

Area-Aware Decomposition for Single-Electron Transistor Arrays

Authors:

Ching-Hsuan Ho,

Yung-Chih Chen,

Ching-Yi Huang,

Vijaykrishnan NarayananAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 4

Article No.: 70, Pages 1 - 20

https://doi.org/10.1145/2898998

Published: 14 September 2016 Publication History

Abstract

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultra-low power consumption. Existing SET synthesis methods synthesize a Boolean network into a large reconfigurable SET array where the height of SET array equals the number of primary inputs. However, recent experiments on device level have shown that this height is restricted to a small number, say, 10, rather than arbitrary value due to the ultra-low driving strength of SET devices. On the other hand, the width of an SET array is also suggested to be a small value. Consequently, it is necessary to decompose a large SET array into a set of small SET arrays where each of them realizes a sub-function of the original circuit with no more than 10 inputs. Thus, this article presents two techniques for achieving area-efficient SET array decomposition: One is a width minimization algorithm for reducing the area of a single SET array; the other is a depth-bounded mapping algorithm, which decomposes a Boolean network into many sub-functions such that the widths of the corresponding SET arrays are balanced. The width minimization algorithm leads to a 25%--41% improvement compared to the state of the art, and the mapping algorithm achieves a 60% reduction in total area compared to a naïve approach.

References

[1]

Randal E. Bryant. 1986. Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput. C-35, 8 (Aug. 1986), 677--691.

Digital Library

[2]

Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, and Vijaykrishnan Narayanan. 2011. Automated mapping for reconfigurable single-electron transistor arrays. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE. 878--883.

Digital Library

[3]

Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, and Vijaykrishnan Narayanan. 2013a. A synthesis algorithm for reconfigurable single-electron transistor arrays. J. Emerg. Technol. Comput. Syst. 9, 1, Article 5 (Feb. 2013).

Digital Library

[4]

Yung-Chih Chen, Chun-Yao Wang, and Ching-Yi Huang. 2013b. Verification of reconfigurable binary decision diagram-based single-electron transistor arrays. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 32, 10 (Oct. 2013), 1473--1483.

Digital Library

[5]

Yi-Hang Chen, Jian-Yu Chen, and Juinn-Dar Huang. 2014. Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. 1--4.

Digital Library

[6]

Yi-Hang Chen, Yang Chen, and Juinn-Dar Huang. 2015. ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays. In 2015 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). 1--4.

[7]

Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, and Vijaykrishnan Narayanan. 2013. On reconfigurable single-electron transistor arrays synthesis using reordering techniques. In Design, Automation Test in Europe Conference Exhibition (DATE), 2013. 1807--1812.

Digital Library

[8]

Jason Cong, Chang Wu, and Yuzheng Ding. 1999. Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution. In Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA’99). ACM, New York, NY, 29--35.

Digital Library

[9]

Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, and Haigang Yang. 2013. Timing-constrained minimum area/power FPGA memory mapping. In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL). 1--4.

[10]

Soumya Eachempati, Vinay Saripalli, Vijaykrishnan Narayanan, and Suman. Datta. 2008. Reconfigurable BDD based quantum circuits. In IEEE International Symposium on Nanoscale Architectures, 2008 (NANOARCH 2008). 61--67.

Digital Library

[11]

Görschwin Fey and Rolf Drechsler. 2006. Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 25, 1 (Jan. 2006), 4--11. 10.1109/TCAD.2005.852662

Digital Library

[12]

Anandaroop Ghosh, Somnath Paul, Jongsun Park, and Swarup Bhunia. 2014. Improving energy efficiency in FPGA through judicious mapping of computation to embedded memory blocks. IEEE Trans. VLSI Syst. 22, 6 (Jun. 2014), 1314--1327.

[13]

Berkeley LSV Group. 2007. ABC: A System for Sequential Synthesis and Verification. (Sep. 2007). Retrieved May 7, 2015 from http://www.eecs.berkeley.edu/&sim;alanmi/abc/.

[14]

Hideki Hasegawa and Seiya Kasai. 2001. Hexagonal binary decision diagram quantum logic circuits using schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires. Physica Es 11, 2--3 (2001), 149--154.

[15]

Karel Heyse, Karel Bruneel, and Dirk Stroobandt. 2012. Mapping logic to reconfigurable FPGA routing. In 2012 22nd International Conference on Field Programmable Logic and Applications (FPL). 315--321.

[16]

IWLS. 2005. IWLS 2005 Benchmarks. (June 2005). Retrieved March, 2015 from http://iwls.org/iwls2005/benchmarks.html.

[17]

Seiya Kasai, M. Yumoto, and Hideki Hasegawa. 2001. Fabrication of GaAs-based integrated 2-bit half and full adders by novel hexagonal BDD quantum circuit approach. In 2001 International Semiconductor Device Research Symposium. 622--625.

[18]

Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, and Vijaykrishnan Narayanan. 2015. Synthesis for width minimization in the single-electron transistor array. IEEE Trans. VLSI Syst. 23, 12 (Dec. 2015), 2862--2875. 10.1109/TVLSI.2014.2386331

[19]

Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, and Vijaykrishnan Narayanan. 2014. Width minimization in the single-electron transistor array synthesis. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. 1--4.

Digital Library

[20]

Lu Liu, Xueqing Li, V. Narayanan, and S. Datta. 2015. A reconfigurable low-power BDD logic architecture using ferroelectric single-electron transistors. IEEE Trans. Electron. Device. 62, 3 (Mar. 2015), 1052--1057.

[21]

Lu Liu, Vijay Narayanan, and Suman Datta. 2013. A programmable ferroelectric single electron transistor. Appl. Phys. Lett. 102, 053505 (2013), 1--4.

[22]

Lu Liu, Vinay Saripalli, Euichul Hwang, Vijaykrishnan Narayanan, and Suman Datta. 2011. Multi-gate modulation doped In0.7Ga0.3 as quantum well FET for ultra low power digital logic. ECS Trans. 35, 3 (2011), 311--317.

[23]

Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic. 2006. Heuristics for area minimization in LUT-based FPGA technology mapping. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 25, 11 (Nov. 2006), 2331--2340.

Digital Library

[24]

Alan Mishchenko, Satrajit Chatterjee, and Robert K. Brayton. 2007a. Improvements to technology mapping for LUT-based FPGAs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 26, 2 (Feb. 2007), 240--253.

Digital Library

[25]

Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, and Robert Brayton. 2007b. Combinational and sequential mapping with priority cuts. In IEEE/ACM International Conference on Computer-Aided Design, 2007 (ICCAD 2007). 354--361.

Digital Library

[26]

Henk W. Ch. Postma, Tijs Teepen, Zhen Yao, Milena Grifoni, and Cees Dekker. 2001. Carbon nanotube single-electron transistors at room temperature. Science 293, 5527 (2001), 76--79. 10.1126/science.1061797

[27]

Vinay Saripalli, Lu Liu, Suman Datta, and Vijaykrishnan Narayanan. 2010. Energy-delay performance of nanoscale transistors exhibiting single electron behavior and associated logic circuits. J. Low Power Electron. 6, 3 (2010), 415--428.

[28]

Fabio Somenzi. 2009. CUDD: CU decision diagram package - release 2.4.2. (2009). Retrieved May 25, 2015 from http://vlsi.colorado.edu/&sim;fabio/CUDD/.

[29]

V. L. Souza and A. G. Silva-Filho. 2013. MogaMap: An application of multi-objective genetic algorithm for LUT-based FPGA technology mapping. In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, Washington, DC, 485--488. 10.1109/ICECS.2013.6815459

[30]

Y. T. Tan, T. Kamiya, Z. A. K. Durrani, and H. Ahmed. 2003. Room temperature nanocrystalline silicon single-electron transistors. J. Appl. Phys. 94, 1 (2003).

[31]

Eric W. Weisstein. 1999. Mixed Graph. (1999). Retrieved June 2, 2015 from http://mathworld.wolfram.com/ MixedGraph.html From MathWorld--A Wolfram Web Resource.

[32]

Zheng Zhao, Chian-Wei Liu, Chun-Yao Wang, and Weikang Qian. 2014. BDD-based synthesis of reconfigurable single-electron transistor arrays. In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). ACM, New York, NY, 47--54.

Digital Library

[33]

Lei Zhuang, Lingjie Guo, and Stephen Y. Chou. 1998. Silicon single-electron quantum-dot transistor switch operating at room temperature. Appl. Phys. Lett. 72, 10 (1998).

Cited By

Wu CHu YLin CChen YHuang JWang C(2021)Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect ModelACM Journal on Emerging Technologies in Computing Systems10.1145/344475117:2(1-23)Online publication date: 21-Jan-2021
https://dl.acm.org/doi/10.1145/3444751
Wu CHo KHuang JWang C(2018)Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00055(257-262)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00055
Li YHuang CWu CChen YWang CDatta SNarayanan V(2017)Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor ArraysIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263953325:4(1477-1489)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2639533

Index Terms

Area-Aware Decomposition for Single-Electron Transistor Arrays
1. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging tools and methodologies
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 4

September 2016

423 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2939671

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2016 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 14 September 2016

Accepted: 01 February 2016

Revised: 01 December 2015

Received: 01 September 2015

Published in TODAES Volume 21, Issue 4

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National Tsing Hua University
Ministry of Science and Technology of Taiwan

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Cited By

Wu CHu YLin CChen YHuang JWang C(2021)Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect ModelACM Journal on Emerging Technologies in Computing Systems10.1145/344475117:2(1-23)Online publication date: 21-Jan-2021
https://dl.acm.org/doi/10.1145/3444751
Wu CHo KHuang JWang C(2018)Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00055(257-262)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00055
Li YHuang CWu CChen YWang CDatta SNarayanan V(2017)Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor ArraysIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263953325:4(1477-1489)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2639533

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