research-article

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Authors:

Hai (Helen) Li,

Bingsheng HeAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 4

Article No.: 71, Pages 1 - 26

https://doi.org/10.1145/2901295

Published: 18 May 2016 Publication History

Abstract

While traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used modules can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time, and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this article, we propose a library-based placement and routing flow that best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in the B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 65% on average with 17% area and 8.2% delay overhead compared with the fine-grained results of Versatile Place and Route through the reuse of module information in the library for the base architecture. For other architectures, the area increase ranges from 8.32% to 25.79%, the delay varies from − 13.66% to 19.79%, and the runtime improves by 43.31% to 77.2%.

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Cited By

Sadeghi AZolfy Lighvan MPrinetto P(2020)Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic AlgorithmCanadian Journal of Electrical and Computer Engineering10.1109/CJECE.2019.296214743:4(224-234)Online publication date: Dec-2021
https://doi.org/10.1109/CJECE.2019.2962147
Mao FZhang WHe BLam S(2017)Dynamic module partitioning for library based placement on heterogeneous FPGAs2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA.2017.8046336(1-6)Online publication date: Aug-2017
https://doi.org/10.1109/RTCSA.2017.8046336
Mao FZhang WHe BLam S(2017)Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2017.61(194-194)Online publication date: May-2017
https://doi.org/10.1109/FCCM.2017.61

Index Terms

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration
1. Hardware
  1. Electronic design automation
    1. Methodologies for EDA
      1. Software tools for EDA
    2. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 4

September 2016

423 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2939671

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

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Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 18 May 2016

Accepted: 01 March 2016

Revised: 01 November 2015

Received: 01 June 2015

Published in TODAES Volume 21, Issue 4

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Cited By

Sadeghi AZolfy Lighvan MPrinetto P(2020)Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic AlgorithmCanadian Journal of Electrical and Computer Engineering10.1109/CJECE.2019.296214743:4(224-234)Online publication date: Dec-2021
https://doi.org/10.1109/CJECE.2019.2962147
Mao FZhang WHe BLam S(2017)Dynamic module partitioning for library based placement on heterogeneous FPGAs2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA.2017.8046336(1-6)Online publication date: Aug-2017
https://doi.org/10.1109/RTCSA.2017.8046336
Mao FZhang WHe BLam S(2017)Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2017.61(194-194)Online publication date: May-2017
https://doi.org/10.1109/FCCM.2017.61

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