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2020 – today
- 2023
[j9]Haoxing Ren
, Brucek Khailany, Matthew Fojtik, Yanqing Zhang:
Machine Learning and Algorithms: Let Us Team Up for EDA. IEEE Des. Test 40(1): 70-76 (2023)- [c22]Chia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren:
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. ISPD 2023: 44-52 - 2021
- [j8]Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler:
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - [c21]Haoxing Ren, Matthew Fojtik:
Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes. ASP-DAC 2021: 684-689 - [c20]Haoxing Ren, Matthew Fojtik:
Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning. DAC 2021: 1291-1294 - [i1]Haoxing Ren, Matthew Fojtik, Brucek Khailany:
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning. CoRR abs/2107.07044 (2021) - 2020
- [j7]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020)
2010 – 2019
- 2019
- [c19]Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany:
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC 2019: 27-35 - [c18]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c17]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany:
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c16]Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler:
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c15]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - 2018
- [c14]Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray:
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC 2018: 1-8 - [c13]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer:
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - 2016
- [j6]Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray:
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. IEEE J. Solid State Circuits 51(2): 557-567 (2016) - [c12]Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun:
Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. ASYNC 2016: 75-82 - [c11]John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally:
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. ISSCC 2016: 156-157 - 2015
- [c10]Ben Keller, Matthew Fojtik, Brucek Khailany:
A Pausible Bisynchronous FIFO for GALS Systems. ASYNC 2015: 1-8 - 2013
- [j5]Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Centip3De: a many-core prototype exploring 3D integration and near-threshold computing. Commun. ACM 56(11): 97-104 (2013) - [j4]Matthew Fojtik, David Fick, Yejoong Kim, Nathaniel Ross Pinckney, David Money Harris, David T. Blaauw, Dennis Sylvester:
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. IEEE J. Solid State Circuits 48(1): 66-81 (2013) - [j3]David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester:
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. IEEE J. Solid State Circuits 48(1): 104-117 (2013) - [j2]Matthew Fojtik, Daeyeon Kim, Gregory K. Chen, Yu-Shiang Lin, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, David T. Blaauw, Dennis Sylvester:
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells. IEEE J. Solid State Circuits 48(3): 801-813 (2013) - [j1]Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Centip3De: A 64-Core, 3D Stacked Near-Threshold System. IEEE Micro 33(2): 8-16 (2013) - [c9]Bharan Giridhar, Matthew Fojtik, David Fick, Dennis Sylvester, David T. Blaauw:
Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating. CICC 2013: 1-4 - 2012
- [c8]Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Centip3De: A 64-core, 3D stacked, near-threshold system. Hot Chips Symposium 2012: 1-30 - [c7]David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. ISSCC 2012: 190-192 - [c6]Matthew Fojtik, David Fick, Yejoong Kim, Nathaniel Ross Pinckney, David Money Harris, David T. Blaauw, Dennis Sylvester:
Bubble Razor: An architecture-independent approach to timing-error detection and correction. ISSCC 2012: 488-490 - [c5]Yen-Po Chen, Matthew Fojtik, David T. Blaauw, Dennis Sylvester:
A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold. VLSIC 2012: 200-201 - 2011
- [c4]Daeyeon Kim, Gregory K. Chen, Matthew Fojtik, Mingoo Seok, David T. Blaauw, Dennis Sylvester:
A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme. ISCAS 2011: 69-72 - 2010
- [c3]David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik, Jae-sun Seo, Dennis Sylvester, David T. Blaauw:
In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter. ISSCC 2010: 188-189 - [c2]Prashant Singh, Zhiyoong Foo, Michael Wieckowski, Scott Hanson, Matthew Fojtik, David T. Blaauw, Dennis Sylvester:
Early detection of oxide breakdown through in situ degradation sensing. ISSCC 2010: 190-191 - [c1]Gregory K. Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis Sylvester, David T. Blaauw:
Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells. ISSCC 2010: 288-289
Coauthor Index
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