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ORCIDCecilia Metra
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- affiliation: University of Bologna, Italy
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2020 – today
- 2024
[c98]Martin Omaña, A. Manfredi, Cecilia Metra, R. Locatelli, M. Chiavacci, S. Petrucci:
Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors' Caches. IOLTS 2024: 1-6- [c97]Sara Cretí, Martin Omaña, Cecilia Metra, Gianni Borelli:
Reliability of AI in Predicting the State of Health of Li-Ion Batteries*. IOLTS 2024: 1-7 - [c96]M. Zhupa, M. Naldi, Maira Omaña, Cecilia Metra:
On the Reliability of Clock Monitoring Units for Safety Critical Applications' Microcontrollers. IOLTS 2024: 1-3 - 2023
- [c95]William Fornaciari, Federico Reghenzani, Federico Terraneo, Davide Baroffio
, Cecilia Metra, Martin Omaña, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Robert Birke, Iacopo Colonnelli, Gianluca Mittone, Marco Aldinucci, Gabriele Mencagli, Francesco Iannone, Filippo Palombi, Giuseppe Zummo, Daniele Cesarini, Federico Tesser:
RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters. SAMOS 2023: 395-410 - 2022
- [j65]Martin Omaña, Sejuti Bardhan, Cecilia Metra:
Reliability Risks Due to Faults Affecting Selectors of ReRAMs and Possible Solutions. IEEE Trans. Emerg. Top. Comput. 10(4): 2086-2091 (2022) - [c94]Marco Grossi, Martin Omaña, Daniele Rossi, Biagio Marzulli, Cecilia Metra:
Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function. IOLTS 2022: 1-7 - [c93]Fabrizio Finelli, Martin Omaña, Cecilia Metra:
Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection. LATS 2022: 1-6 - 2020
- [j64]Cecilia Metra, Matteo Sonza Reorda:
Guest Editor's Introduction: Special Section on High Dependability Systems. IEEE Trans. Emerg. Top. Comput. 8(2): 416-417 (2020) - [j63]Cecilia Metra:
Message from the Editor-in-Chief. IEEE Trans. Emerg. Top. Comput. 8(4): 885-886 (2020)
2010 – 2019
- 2019
- [j62]Cecilia Metra:
The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence. Computer 52(1): 4-6 (2019) - [j61]Cecilia Metra:
The 2019 IEEE Computer Society: Hit Target on Member Satisfaction and Technical Excellence. Computer 52(12): 4-11 (2019) - [j60]Martin Omaña, S. Govindaraj, Cecilia Metra:
Low-Cost Strategy for Bus Propagation Delay Reduction. J. Electron. Test. 35(2): 253-260 (2019) - [j59]Cecilia Metra:
Message from the Editor-in-Chief. IEEE Trans. Emerg. Top. Comput. 7(1): 3-4 (2019) - [j58]Rob Aitken, Cecilia Metra:
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage. IEEE Trans. Emerg. Top. Comput. 7(3): 433-434 (2019) - [j57]Martin Omaña, Alessandro Fiore, Marco Mongitore, Cecilia Metra:
Fault-Tolerant Inverters for Reliable Photovoltaic Systems. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 20-28 (2019) - 2018
- [j56]Cecilia Metra:
Message from the Editor-in-Chief. IEEE Trans. Emerg. Top. Comput. 6(1): 3-4 (2018) - [j55]Martin Omaña, TusharaSandeep Edara, Cecilia Metra:
Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness. IEEE Trans. Emerg. Top. Comput. 6(4): 488-497 (2018) - 2017
- [j54]Martin Omaña, Marco Padovani, Kreshnik Veliu, Cecilia Metra, Juergen Alt, Rajesh Galivanche:
New Approaches for Power Binning of High Performance Microprocessors. IEEE Trans. Computers 66(7): 1159-1171 (2017) - [j53]Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche:
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 238-246 (2017) - 2016
- [j52]Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche:
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. IEEE Trans. Computers 65(8): 2484-2494 (2016) - [c92]Martin Omaña, A. Fiore, Cecilia Metra:
Inverters' self-checking monitors for reliable photovoltaic systems. DATE 2016: 672-677 - 2015
- [j51]Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam:
Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 435-443 (2015) - [j50]Daniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella:
Impact of Bias Temperature Instability on Soft Error Susceptibility. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 743-751 (2015) - [j49]Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra:
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1031-1039 (2015) - [c91]Michael A. Kochte, Atefe Dalirsani, Andrea Bernabei, Martin Omaña, Cecilia Metra, Hans-Joachim Wunderlich:
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. ATS 2015: 157-162 - 2014
- [j48]Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak:
Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. 30(1): 111-123 (2014) - [c90]Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche:
Power droop reduction during Launch-On-Shift scan-based logic BIST. DFT 2014: 21-26 - 2013
- [j47]Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche:
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. J. Electron. Test. 29(3): 401-413 (2013) - [j46]Martin Omaña, Daniele Rossi, Nicolò Bosio, Cecilia Metra:
Low Cost NBTI Degradation Detection and Masking Approaches. IEEE Trans. Computers 62(3): 496-509 (2013) - [j45]Martin Omaña, Daniele Rossi, Daniele Giaffreda, Roberto Specchia, Cecilia Metra, Marcin Marzencki, Bozena Kaminska:
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2286-2294 (2013) - [c89]Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, R. Galivache:
Novel approach to reduce power droop during scan-based logic BIST. ETS 2013: 1-6 - 2012
- [j44]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
New Design for Testability Approach for Clock Fault Testing. IEEE Trans. Computers 61(4): 448-457 (2012) - [c88]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella:
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT 2012: 121-125 - [c87]Martin Omaña, Daniele Rossi, G. Collepalumbo, Cecilia Metra, Fabrizio Lombardi:
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. DFT 2012: 199-204 - 2011
- [j43]Cecilia Metra, Rajesh Galivanche:
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems. IEEE Trans. Computers 60(9): 1217-1218 (2011) - [j42]Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam:
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2322-2325 (2011) - [c86]Daniele Rossi, N. Timoncini, M. Spica, Cecilia Metra:
Error correcting code analysis for cache memory high reliability and performance. DATE 2011: 1620-1625 - [c85]Daniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella:
Impact of Aging Phenomena on Soft Error Susceptibility. DFT 2011: 18-24 - [c84]Daniele Giaffreda, Martin Omaña, Daniele Rossi, Cecilia Metra:
Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. DFT 2011: 252-258 - 2010
- [j41]Martin Omaña, Daniele Rossi, Cecilia Metra:
High-Performance Robust Latches. IEEE Trans. Computers 59(11): 1455-1465 (2010) - [c83]Martin Omaña, Daniele Rossi, Nicolò Bosio, Cecilia Metra:
Novel low-cost aging sensor. Conf. Computing Frontiers 2010: 93-94 - [c82]Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche:
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers 2010: 113-114 - [c81]Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman:
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. DFT 2010: 265-272 - [c80]Daniele Rossi, Martin Omaña, Cecilia Metra:
Transient Fault and Soft Error On-die Monitoring Scheme. DFT 2010: 391-398 - [c79]Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra:
Secure communication protocol for wireless sensor networks. EWDTS 2010: 17-20
2000 – 2009
- 2009
- [j40]Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi:
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates. J. Electron. Test. 25(1): 39-54 (2009) - [j39]Michele Favalli, Cecilia Metra:
Testing Resistive Opens and Bridging Faults Through Pulse Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 915-925 (2009) - [j38]Daniele Rossi, José Manuel Cazeaux, Martin Omaña, Cecilia Metra, Abhijit Chatterjee:
Accurate Linear Model for SET Critical Charge Estimation. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1161-1166 (2009) - [c78]Martin Omaña, Daniele Rossi, Cecilia Metra:
Novel High Speed Robust Latch. DFT 2009: 65-73 - [c77]Martin Omaña, Marcin Marzencki, Roberto Specchia, Cecilia Metra, Bozena Kaminska:
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors. DFT 2009: 127-135 - 2008
- [j37]Daniele Rossi, André K. Nieuwland, Cecilia Metra:
Simultaneous Switching Noise: The Relation between Bus Layout and Coding. IEEE Des. Test Comput. 25(1): 76-86 (2008) - [j36]Daniele Rossi, Martin Omaña, Cecilia Metra:
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. J. Electron. Test. 24(1-3): 93-103 (2008) - [j35]Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi:
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA. J. Electron. Test. 24(1-3): 297-311 (2008) - [j34]Daniele Rossi, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra:
Power Consumption of Fault Tolerant Busses. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 542-553 (2008) - [c76]Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam:
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT 2008: 465-473 - [c75]Daniele Rossi, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gian Pietro Vanalli:
Risks for Signal Integrity in System in Package and Possible Remedies. ETS 2008: 165-170 - [c74]Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche:
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. ETS 2008: 171-176 - 2007
- [j33]Fabrizio Lombardi, Cecilia Metra:
Guest Editors' Introduction: The State of the Art in Nanoscale CAD. IEEE Des. Test Comput. 24(4): 302-303 (2007) - [j32]Cecilia Metra, Daniele Rossi, T. M. Mak:
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers 56(3): 415-428 (2007) - [j31]Martin Omaña, Daniele Rossi, Cecilia Metra:
Latch Susceptibility to Transient Faults and New Hardening Approach. IEEE Trans. Computers 56(9): 1255-1268 (2007) - [c73]Michele Favalli, Cecilia Metra:
Interactive presentation: Pulse propagation for the detection of small delay defects. DATE 2007: 1295-1300 - [c72]Jing Huang, Xiaojun Ma, Cecilia Metra, Fabrizio Lombardi:
Testing Reversible One-Dimensional QCA Arrays for Multiple Faults. DFT 2007: 469-477 - [c71]Daniele Rossi, Paolo Angelini, Cecilia Metra:
Configurable Error Control Scheme for NoC Signal Integrity. IOLTS 2007: 43-48 - [c70]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
Novel compensation scheme for local clocks of high performance microprocessors. ITC 2007: 1-9 - [c69]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS 2007: 441-446 - 2006
- [j30]Jien-Chung Lo, Cecilia Metra, Fabrizio Lombardi:
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). IEEE Trans. Computers 55(2): 97-98 (2006) - [c68]Daniele Rossi, Carlo Steiner, Cecilia Metra:
Analysis of the impact of bus implemented EDCs on on-chip SSN. DATE 2006: 59-64 - [c67]Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra:
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. DATE 2006: 170-175 - [c66]Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak:
Can Clock Faults be Detected Through Functional Test? DDECS 2006: 168-173 - [c65]Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi:
Testing Reversible 1D Arrays for Molecular QCA. DFT 2006: 71-79 - [c64]Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak:
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS 2006: 17-22 - [c63]Daniele Rossi, Martin Omaña, Cecilia Metra, Andrea Pagni:
Checker No-Harm Alarm Robustness. IOLTS 2006: 275-280 - 2005
- [j29]Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra:
Exploiting ECC Redundancy to Minimize Crosstalk Impact. IEEE Des. Test Comput. 22(1): 59-70 (2005) - [j28]Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra:
New ECC for Crosstalk Impact Minimization. IEEE Des. Test Comput. 22(4): 340-348 (2005) - [j27]José Manuel Cazeaux, Daniele Rossi, Cecilia Metra:
Self-Checking Voter for High Speed TMR Systems. J. Electron. Test. 21(4): 377-389 (2005) - [j26]Martin Omaña, Daniele Rossi, Cecilia Metra:
Low Cost and High Speed Embedded Two-Rail Code Checker. IEEE Trans. Computers 54(2): 153-164 (2005) - [j25]José Manuel Cazeaux, Martin Omaña, Cecilia Metra:
Novel on-chip circuit for jitter testing in high-speed PLLs. IEEE Trans. Instrum. Meas. 54(5): 1779-1788 (2005) - [c62]Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak:
The Other Side of the Timing Equation: a Result of Clock Faults. DFT 2005: 169-177 - [c61]Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra:
Multiple Transient Faults in Logic: An Issue for Next Generation ICs. DFT 2005: 352-360 - [c60]José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee:
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. IOLTS 2005: 23-28 - [c59]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra:
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. IOLTS 2005: 35-40 - [c58]Martin Omaña, O. Losco, Cecilia Metra, Andrea Pagni:
On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. IOLTS 2005: 163-168 - [c57]André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra:
Coding Techniques for Low Switching Noise in Fault Tolerant Busses. IOLTS 2005: 183-189 - [c56]Martin Omaña, Daniele Rossi, Cecilia Metra:
Low Cost Scheme for On-Line Clock Skew Compensation. VTS 2005: 90-95 - 2004
- [j24]André Ivanov, Fabrizio Lombardi, Cecilia Metra:
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates. IEEE Des. Test Comput. 21(4): 274-276 (2004) - [j23]Cecilia Metra, Matteo Sonza Reorda:
Guest Editorial. J. Electron. Test. 20(5): 463 (2004) - [j22]Martin Omaña, Daniele Rossi, Cecilia Metra:
Model for Transient Fault Susceptibility of Combinational Circuits. J. Electron. Test. 20(5): 501-509 (2004) - [j21]Cecilia Metra, Stefano Di Francescantonio, T. M. Mak:
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers 53(5): 531-546 (2004) - [j20]Michele Favalli, Cecilia Metra:
TMR voting in the presence of crosstalk faults at the voter inputs. IEEE Trans. Reliab. 53(3): 342-348 (2004) - [c55]Cecilia Metra, T. M. Mak, Martin Omaña:
Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers 2004: 444-450 - [c54]Cecilia Metra, T. M. Mak, Martin Omaña:
Are Our Design for Testability Features Fault Secure? DATE 2004: 714-715 - [c53]Martin Omaña, Daniele Rossi, Cecilia Metra:
Fast and Low-Cost Clock Deskew Buffer. DFT 2004: 202-210 - [c52]José Manuel Cazeaux, Martin Omaña, Cecilia Metra:
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. IOLTS 2004: 17-24 - [c51]José Manuel Cazeaux, Daniele Rossi, Cecilia Metra:
New High Speed CMOS Self-Checking Voter. IOLTS 2004: 58-66 - [c50]Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra:
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. IOLTS 2004: 135-140 - [c49]Cecilia Metra, A. Ferrari, Martin Omaña, Andrea Pagni:
Hardware Reconfiguration Scheme for High Availability Systems. IOLTS 2004: 161-166 - [c48]Cecilia Metra, T. M. Mak, Martin Omaña:
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC 2004: 1223-1231 - 2003
- [j19]Cecilia Metra, Matteo Sonza Reorda:
Guest Editorial. J. Electron. Test. 19(5): 499 (2003) - [j18]Daniele Rossi, Cecilia Metra:
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories. J. Electron. Test. 19(5): 511-521 (2003) - [j17]Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò:
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. Microelectron. J. 34(1): 23-29 (2003) - [j16]Luca Schiano, Cecilia Metra, Diego Marino:
Self-checking design, implementation, and measurement of a controller for track-side railway systems. IEEE Trans. Instrum. Meas. 52(6): 1722-1728 (2003) - [j15]Cecilia Metra, Luca Schiano, Michele Favalli:
Concurrent detection of power supply noise. IEEE Trans. Reliab. 52(4): 469-475 (2003) - [c47]Martin Omaña, Daniele Rossi, Cecilia Metra:
High Speed and Highly Testable Parallel Two-Rail Code Checker. DATE 2003: 10608-10615 - [c46]Cecilia Metra, T. M. Mak, Daniele Rossi:
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT 2003: 63-70 - [c45]Daniele Rossi, S. Cavallotti, Cecilia Metra:
Error Correcting Codes for Crosstalk Effect Minimization. DFT 2003: 257- - [c44]Cecilia Metra, Stefano Di Francescantonio, Martin Omaña:
Automatic Modification of Sequential Circuits for Self-Checking Implementation. DFT 2003: 417-424 - [c43]Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra:
Power Consumption of Fault Tolerant Codes: the Active Elements. IOLTS 2003: 61-67 - [c42]Martin Omaña, Giacinto Papasso, Daniele Rossi, Cecilia Metra:
A Model for Transient Fault Propagation in Combinatorial Logic. IOLTS 2003: 111- - [c41]L. Di Silvio, Daniele Rossi, Cecilia Metra:
Crosstalk Effect Minimization for Encoded Busses. IOLTS 2003: 214-218 - [c40]Martin Omaña, Daniele Rossi, Cecilia Metra:
Novel Transient Fault Hardened Static Latch. ITC 2003: 886-892 - 2002
- [j14]Michele Favalli, Cecilia Metra:
Online Testing Approach for Very Deep-Submicron ICs. IEEE Des. Test Comput. 19(2): 16-23 (2002) - [j13]Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra:
Guest Editorial. J. Electron. Test. 18(3): 259-260 (2002) - [j12]Michele Favalli, Cecilia Metra:
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. J. Electron. Test. 18(3): 273-283 (2002) - [j11]Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò:
On-Chip Clock Faults' Detector. J. Electron. Test. 18(4-5): 555-564 (2002) - [c39]Michele Favalli, Cecilia Metra:
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. DATE 2002: 612-617 - [c38]Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli:
Self-Checking Scheme for the On-Line Testing of Power Supply Noise. DATE 2002: 832-836 - [c37]Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale:
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. DFT 2002: 207-215 - [c36]Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra:
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. IOLTW 2002: 8-12 - [c35]Daniele Rossi, Cecilia Metra, Bruno Riccò:
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. IOLTW 2002: 221-225 - [c34]Luca Schiano, Cecilia Metra, Diego Marino:
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. IOLTW 2002: 243- - [c33]Cecilia Metra, Stefano Di Francescantonio, T. M. Mak:
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC 2002: 100-109 - [c32]Daniele Rossi, Cecilia Metra, Bruno Riccò:
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. MTDT 2002: 27-31 - [c31]Luca Schiano, Cecilia Metra, Diego Marino:
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. MTDT 2002: 49-56 - 2001
- [j10]Fabrizio Lombardi, Cecilia Metra:
Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems. IEEE Des. Test Comput. 18(1): 8-9 (2001) - [c30]Michele Favalli, Cecilia Metra:
Optimization of error detecting codes for the detection of crosstalk originated errors. DATE 2001: 290-296 - [c29]Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak:
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT 2001: 357-365 - [c28]Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra:
Novel Fault-Tolerant Adder Design for FPGA-Based Systems. IOLTW 2001: 54- - [c27]Michele Favalli, Cecilia Metra:
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. IOLTW 2001: 100-105 - [c26]Cecilia Metra, Andrea Pagano, Bruno Riccò:
On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems. ITC 2001: 939-947 - 2000
- [j9]Cecilia Metra, Jien-Chung Lo:
Intermediacy Prediction for High Speed Berger Code Checkers. J. Electron. Test. 16(6): 607-615 (2000) - [j8]Michele Favalli, Cecilia Metra:
Bridging Faults in Pipelined Circuits. J. Electron. Test. 16(6): 617-629 (2000) - [j7]Cecilia Metra, Michele Favalli, Bruno Riccò:
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. IEEE Trans. Computers 49(6): 560-574 (2000) - [j6]Cecilia Metra, Michele Favalli, Bruno Riccò:
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits. VLSI Design 11(1): 23-34 (2000) - [c25]Cecilia Metra, Michele Favalli, Bruno Riccò:
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. DATE 2000: 763 - [c24]Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra:
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. DFT 2000: 155-163
1990 – 1999
- 1999
- [j5]Michele Favalli, Cecilia Metra:
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 392-396 (1999) - [c23]Michele Favalli, Cecilia Metra:
On the Design of Self-Checking Functional Units Based on Shannon Circuits. DATE 1999: 368-375 - [c22]Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra:
Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. DFT 1999: 330-338 - [c21]Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò:
Self-checking scheme for very fast clocks' skew correction. ITC 1999: 652-661 - 1998
- [j4]Cecilia Metra, Michele Favalli, Bruno Riccò:
Concurrent Checking of Clock Signal Correctness. IEEE Des. Test Comput. 15(4): 42-48 (1998) - [c20]Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi:
Novel Technique for Testing FPGAs. DATE 1998: 89-94 - [c19]Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n Code Checker with Single Output. DATE 1998: 981-982 - [c18]Cecilia Metra, Michele Favalli, Bruno Riccò:
Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. DFT 1998: 174-182 - [c17]Sergio D'Angelo, Cecilia Metra, Sandro Pastore, A. Pogutz, Giacomo R. Sechi:
Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems. DFT 1998: 233-240 - [c16]Cecilia Metra, Michele Favalli, Bruno Riccò:
On-line detection of logic errors due to crosstalk, delay, and transient faults. ITC 1998: 524-533 - 1997
- [j3]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 770-776 (1997) - [c15]Michele Favalli, Cecilia Metra:
Testing scheme for IC's clocks. ED&TC 1997: 445-449 - [c14]Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra:
Fast and area-time efficient Berger code checkers. DFT 1997: 110-118 - [c13]Cecilia Metra, Michele Favalli, Bruno Riccò:
Compact and low power on-line self-testing voting scheme. DFT 1997: 137-147 - [c12]Michele Favalli, Cecilia Metra:
Low-level error recovery mechanism for self-checking sequential circuits. DFT 1997: 234-242 - [c11]Cecilia Metra, Michele Favalli, Bruno Riccò:
On-Line Testing Scheme for Clock's Faults. ITC 1997: 587-596 - [c10]Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly testable and compact single output comparator. VTS 1997: 210-215 - 1996
- [j2]Michele Favalli, Cecilia Metra:
Sensing circuit for on-line detection of delay faults. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 130-133 (1996) - [c9]Cecilia Metra, Michele Favalli, Bruno Riccò:
Compact and Highly Testable Error Indicator for Self-Checking Circuits. DFT 1996: 204-212 - [c8]Cecilia Metra, Michele Favalli, Bruno Riccò:
Tree Checkers for Applications with Low Power-Delay Requirements. DFT 1996: 213-220 - [c7]Cecilia Metra, Michele Favalli, Bruno Riccò:
Embedded two-rail checkers with on-line testing ability. VTS 1996: 145-150 - 1995
- [j1]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. J. Electron. Test. 6(1): 7-22 (1995) - [c6]Cecilia Metra, Michele Favalli, Bruno Riccò:
Novel Berger code checker. DFT 1995: 287-295 - 1994
- [c5]Cecilia Metra, Michele Favalli, Bruno Riccò:
CMOS Self Checking Circuits with Faulty Sequential Functional Block. DFT 1994: 133-141 - [c4]Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n CMOS Checkers. DFT 1994: 142-150 - 1993
- [c3]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. DFT 1993: 271-278 - [c2]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
A Highly Testable 1-out-of-3 CMOS Checker. DFT 1993: 279-286 - 1992
- [c1]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. ITC 1992: 948-957
Coauthor Index
[c98] [c97] [c95] [j65] [c94] [c93] [j60] [j57] [j55] [j54] [j53] [j52] [c92] [j51] [j50] [j49] [c91] [j48] [c90] [j47] [j46] [j45] [c89] [j44] [c88] [c87] [j42] [c85] [c84] [j41] [c83] [c82] [c81] [c80] [c79] [j38] [c78] [c77] [j36] [c76] [c74] [j31] [c70] [c69] [c67] [c66] [c64] [c63] [j26] [j25] [c62] [c61] [c60] [c58] [c56] [j22] [c55] [c54] [c53] [c52] [c49] [c48] [c47] [c44] [c42] [c40]
[c94] [j53] [j52] [j51] [j50] [j49] [j48] [c90] [j47] [j46] [j45] [c89] [c88] [c87] [c86] [c85] [c84] [j41] [c83] [c82] [c80] [c79] [j38] [c78] [j37] [j36] [j34] [c75] [c74] [j32] [j31] [c71] [c68] [c67] [c66] [c64] [c63] [j29] [j28] [j27] [j26] [c62] [c61] [c60] [c57] [c56] [j22] [c53] [c51] [c50] [j18] [c47] [c46] [c45] [c43] [c42] [c41] [c40] [c36] [c35] [c32]
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